riscv/rocket-chip
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remove ext_mem interface

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hindsight is 20/20
This commit is contained in:
Andrew Waterman 2012-02-26 18:53:39 -08:00
parent 2d04664a98
commit e12b9eae93
4 changed files with 21 additions and 52 deletions
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2
rocket/src/main/scala/consts.scala
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@ -164,7 +164,7 @@ object Constants
val PERM_BITS = 6;
// rocketNBDCache parameters
val DCACHE_PORTS = 2
val DCACHE_PORTS = 3
val CPU_DATA_BITS = 64;
val CPU_TAG_BITS = 9;
val DCACHE_TAG_BITS = log2up(DCACHE_PORTS) + CPU_TAG_BITS

12
rocket/src/main/scala/cpu.scala
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@ -96,9 +96,6 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
arb.io.requestor(0).req_ppn := dtlb.io.cpu_resp.ppn;
ctrl.io.dmem.req_rdy := dtlb.io.cpu_req.ready && arb.io.requestor(0).req_rdy;
// connect DTLB to D$ arbiter
ctrl.io.xcpt_ma_ld := io.dmem.xcpt_ma_ld
ctrl.io.xcpt_ma_st := io.dmem.xcpt_ma_st
// connect page table walker to TLBs, page table base register (from PCR)
// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
ptw.io.dtlb <> dtlb.io.ptw;
@ -194,7 +191,8 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
vu.io.cpu_exception.exception := dpath.io.vec_iface.exception
// hooking up vector memory interface
ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid
//arb.io.requestor(2) <> vu.io.dmem_req
/*ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid
ctrl.io.ext_mem.req_cmd := vu.io.dmem_req.bits.cmd
ctrl.io.ext_mem.req_type := vu.io.dmem_req.bits.typ
@ -208,7 +206,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
vu.io.dmem_resp.bits.nack := ctrl.io.ext_mem.resp_nack
vu.io.dmem_resp.bits.data := dpath.io.ext_mem.resp_data
vu.io.dmem_resp.bits.tag := dpath.io.ext_mem.resp_tag
vu.io.dmem_resp.bits.typ := dpath.io.ext_mem.resp_type
vu.io.dmem_resp.bits.typ := dpath.io.ext_mem.resp_type*/
// share vector integer multiplier with rocket
dpath.io.vec_imul_req <> vu.io.cp_imul_req
@ -219,9 +217,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
}
else
{
ctrl.io.ext_mem.req_val := Bool(false)
dpath.io.ext_mem.req_val := Bool(false)
arb.io.requestor(2).req_val := Bool(false)
if (HAVE_FPU)
{
fpu.io.sfma.valid := Bool(false)

35
rocket/src/main/scala/ctrl.scala
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@ -35,7 +35,6 @@ class ioCtrlDpath extends Bundle()
val id_eret = Bool(OUTPUT);
val wb_eret = Bool(OUTPUT);
val mem_load = Bool(OUTPUT);
val ex_ext_mem_val = Bool(OUTPUT);
val ex_fp_val= Bool(OUTPUT);
val mem_fp_val= Bool(OUTPUT);
val ex_wen = Bool(OUTPUT);
@ -79,8 +78,7 @@ class ioCtrlAll extends Bundle()
{
val dpath = new ioCtrlDpath();
val imem = new ioImem(List("req_val", "resp_val")).flip();
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack")).flip();
val ext_mem = new ioDmem(List("req_val", "req_cmd", "req_type", "resp_nack"))
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack", "xcpt_ma_ld", "xcpt_ma_st")).flip();
val dtlb_val = Bool(OUTPUT);
val dtlb_kill = Bool(OUTPUT);
val dtlb_rdy = Bool(INPUT);
@ -88,8 +86,6 @@ class ioCtrlAll extends Bundle()
val xcpt_dtlb_ld = Bool(INPUT);
val xcpt_dtlb_st = Bool(INPUT);
val xcpt_itlb = Bool(INPUT);
val xcpt_ma_ld = Bool(INPUT);
val xcpt_ma_st = Bool(INPUT);
val fpu = new ioCtrlFPU();
val vec_dpath = new ioCtrlDpathVec()
val vec_iface = new ioCtrlVecInterface()
@ -333,7 +329,6 @@ class rocketCtrl extends Component
val ex_reg_vec_val = Reg(resetVal = Bool(false));
val ex_reg_replay = Reg(resetVal = Bool(false));
val ex_reg_load_use = Reg(resetVal = Bool(false));
val ex_reg_ext_mem_val = Reg(resetVal = Bool(false))
val mem_reg_valid = Reg(resetVal = Bool(false));
val mem_reg_wen_pcr = Reg(resetVal = Bool(false));
@ -352,7 +347,6 @@ class rocketCtrl extends Component
val mem_reg_fp_val = Reg(resetVal = Bool(false));
val mem_reg_replay = Reg(resetVal = Bool(false));
val mem_reg_kill = Reg(resetVal = Bool(false));
val mem_reg_ext_mem_val = Reg(resetVal = Bool(false))
val mem_reg_fp_sboard_set = Reg(resetVal = Bool(false));
val wb_reg_valid = Reg(resetVal = Bool(false));
@ -368,7 +362,6 @@ class rocketCtrl extends Component
val wb_reg_cause = Reg(){UFix()};
val wb_reg_fp_val = Reg(resetVal = Bool(false));
val wb_reg_fp_sboard_set = Reg(resetVal = Bool(false));
val wb_reg_ext_mem_nack = Reg(resetVal = Bool(false))
val take_pc = Wire() { Bool() };
@ -445,11 +438,8 @@ class rocketCtrl extends Component
ex_reg_replay := id_reg_replay
ex_reg_load_use := id_load_use;
}
ex_reg_ext_mem_val := io.ext_mem.req_val
ex_reg_mem_cmd := Mux(io.ext_mem.req_val, io.ext_mem.req_cmd, id_mem_cmd).toUFix
ex_reg_mem_type := Mux(io.ext_mem.req_val, io.ext_mem.req_type, id_mem_type).toUFix
val ex_ext_mem_val = ex_reg_ext_mem_val && !wb_reg_ext_mem_nack
ex_reg_mem_cmd := id_mem_cmd
ex_reg_mem_type := id_mem_type.toUFix
val beq = io.dpath.br_eq;
val bne = ~io.dpath.br_eq;
@ -516,7 +506,6 @@ class rocketCtrl extends Component
mem_reg_fp_val := ex_reg_fp_val
mem_reg_fp_sboard_set := ex_reg_fp_sboard_set
}
mem_reg_ext_mem_val := ex_ext_mem_val
mem_reg_mem_cmd := ex_reg_mem_cmd;
mem_reg_mem_type := ex_reg_mem_type;
@ -546,7 +535,6 @@ class rocketCtrl extends Component
wb_reg_fp_val := mem_reg_fp_val
wb_reg_fp_sboard_set := mem_reg_fp_sboard_set
}
wb_reg_ext_mem_nack := io.ext_mem.resp_nack
val sboard = new rocketCtrlSboard(32, 3, 2);
sboard.io.r(0).addr := id_raddr2.toUFix;
@ -623,8 +611,8 @@ class rocketCtrl extends Component
Mux(p_irq_timer, UFix(23,5),
UFix(0,5)));
val mem_xcpt_ma_ld = io.xcpt_ma_ld && !mem_reg_kill
val mem_xcpt_ma_st = io.xcpt_ma_st && !mem_reg_kill
val mem_xcpt_ma_ld = io.dmem.xcpt_ma_ld && !mem_reg_kill
val mem_xcpt_ma_st = io.dmem.xcpt_ma_st && !mem_reg_kill
val mem_xcpt_dtlb_ld = io.xcpt_dtlb_ld && !mem_reg_kill
val mem_xcpt_dtlb_st = io.xcpt_dtlb_st && !mem_reg_kill
@ -667,7 +655,7 @@ class rocketCtrl extends Component
val dmem_kill_mem = mem_reg_valid && (io.dtlb_miss || io.dmem.resp_nack)
val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay
val kill_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
val kill_dcache = io.dtlb_miss || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill || mem_reg_ext_mem_val && wb_reg_ext_mem_nack
val kill_dcache = io.dtlb_miss || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
// replay execute stage PC when the D$ is blocked, when the D$ misses,
// for privileged instructions, and for fence.i instructions
@ -757,7 +745,7 @@ class rocketCtrl extends Component
(
id_ex_hazard || id_mem_hazard || id_wb_hazard ||
id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
id_stall_fpu || io.ext_mem.req_val ||
id_stall_fpu ||
id_mem_val.toBool && !(io.dmem.req_rdy && io.dtlb_rdy) ||
id_vec_val.toBool && !(io.vec_iface.vcmdq_ready && io.vec_iface.vximm1q_ready && io.vec_iface.vximm2q_ready) || // being conservative
((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
@ -779,14 +767,13 @@ class rocketCtrl extends Component
io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
io.dpath.ren2 := id_renx2.toBool;
io.dpath.ren1 := id_renx1.toBool;
io.dpath.sel_alu2 := Mux(io.ext_mem.req_val, A2_ZERO, id_sel_alu2)
io.dpath.sel_alu2 := id_sel_alu2
io.dpath.fn_dw := id_fn_dw.toBool;
io.dpath.fn_alu := id_fn_alu;
io.dpath.div_fn := id_div_fn;
io.dpath.div_val := id_div_val.toBool;
io.dpath.mul_fn := id_mul_fn;
io.dpath.mul_val := id_mul_val.toBool;
io.dpath.ex_ext_mem_val := ex_ext_mem_val;
io.dpath.ex_fp_val:= ex_reg_fp_val;
io.dpath.mem_fp_val:= mem_reg_fp_val;
io.dpath.ex_wen := ex_reg_wen;
@ -807,12 +794,10 @@ class rocketCtrl extends Component
io.fpu.killx := kill_ex
io.fpu.killm := kill_mem
io.dtlb_val := ex_reg_mem_val || ex_ext_mem_val
io.dtlb_val := ex_reg_mem_val
io.dtlb_kill := mem_reg_kill;
io.dmem.req_val := ex_reg_mem_val || ex_ext_mem_val
io.dmem.req_val := ex_reg_mem_val
io.dmem.req_kill := kill_dcache;
io.dmem.req_cmd := ex_reg_mem_cmd;
io.dmem.req_type := ex_reg_mem_type;
io.ext_mem.resp_nack:= mem_reg_ext_mem_val && !wb_reg_ext_mem_nack && (io.dmem.req_kill || io.dmem.resp_nack || Reg(!io.dmem.req_rdy))
}

24
rocket/src/main/scala/dpath.scala
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@ -20,7 +20,6 @@ class ioDpathAll extends Bundle()
val debug = new ioDebug();
val dmem = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip();
val dtlb = new ioDTLB_CPU_req_bundle(List("vpn"))
val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "req_tag", "resp_val", "resp_data", "resp_type", "resp_tag"))
val imem = new ioDpathImem();
val ptbr_wen = Bool(OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);
@ -73,7 +72,6 @@ class rocketDpath extends Component
val ex_reg_ctrl_div_fn = Reg() { UFix() };
val ex_reg_ctrl_sel_wb = Reg() { UFix() };
val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
val ex_reg_ext_mem_tag = Reg() { Bits() };
val ex_wdata = Wire() { Bits() };
// memory definitions
@ -166,18 +164,16 @@ class rocketDpath extends Component
// bypass muxes
val id_rs1 =
Mux(io.ext_mem.req_val, Cat(io.ext_mem.req_ppn, io.ext_mem.req_idx),
Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, ex_wdata,
Mux(io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr, mem_wdata,
Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
id_rdata1))))
id_rdata1)))
val id_rs2 =
Mux(io.ext_mem.req_val, io.ext_mem.req_data,
Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, ex_wdata,
Mux(io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr, mem_wdata,
Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
id_rdata2))))
id_rdata2)))
// immediate generation
val id_imm_bj = io.ctrl.sel_alu2 === A2_BTYPE || io.ctrl.sel_alu2 === A2_JTYPE
@ -215,7 +211,6 @@ class rocketDpath extends Component
ex_reg_ctrl_div_fn := io.ctrl.div_fn;
ex_reg_ctrl_sel_wb := io.ctrl.sel_wb;
ex_reg_ctrl_ren_pcr := io.ctrl.ren_pcr;
ex_reg_ext_mem_tag := io.ext_mem.req_tag
when(io.ctrl.killd) {
ex_reg_ctrl_div_val := Bool(false);
@ -272,7 +267,7 @@ class rocketDpath extends Component
// other signals (req_val, req_rdy) connect to control module
io.dmem.req_idx := ex_effective_address
io.dmem.req_data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
io.dmem.req_tag := Cat(Mux(io.ctrl.ex_ext_mem_val, ex_reg_ext_mem_tag(CPU_TAG_BITS-2, 0), Cat(ex_reg_waddr, io.ctrl.ex_fp_val)), io.ctrl.ex_ext_mem_val).toUFix
io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val)
io.dtlb.vpn := ex_effective_address >> UFix(PGIDX_BITS)
// processor control regfile read
@ -334,11 +329,9 @@ class rocketDpath extends Component
// 32/64 bit load handling (moved to earlier in file)
// writeback arbitration
val dmem_resp_ext = io.dmem.resp_tag(0).toBool
val dmem_resp_xpu = !io.dmem.resp_tag(0).toBool && !io.dmem.resp_tag(1).toBool
val dmem_resp_fpu = !io.dmem.resp_tag(0).toBool && io.dmem.resp_tag(1).toBool
val dmem_resp_waddr = io.dmem.resp_tag.toUFix >> UFix(2)
val dmem_resp_ext_tag = io.dmem.resp_tag.toUFix >> UFix(1)
val dmem_resp_xpu = !io.dmem.resp_tag(0).toBool
val dmem_resp_fpu = io.dmem.resp_tag(0).toBool
val dmem_resp_waddr = io.dmem.resp_tag.toUFix >> UFix(1)
dmem_resp_replay := io.dmem.resp_replay && dmem_resp_xpu;
r_dmem_resp_replay := dmem_resp_replay
r_dmem_resp_waddr := dmem_resp_waddr
@ -409,11 +402,6 @@ class rocketDpath extends Component
rfile.io.w0.en := io.ctrl.wb_wen || wb_reg_ll_wb
rfile.io.w0.data := wb_wdata
io.ext_mem.resp_val := Reg(io.dmem.resp_val && dmem_resp_ext, resetVal = Bool(false))
io.ext_mem.resp_tag := Reg(dmem_resp_ext_tag)
io.ext_mem.resp_type := Reg(io.dmem.resp_type)
io.ext_mem.resp_data := io.dmem.resp_data_subword
io.ctrl.wb_waddr := wb_reg_waddr
io.ctrl.mem_wb := dmem_resp_replay;