Andrew Waterman
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59f5358435
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Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
|
Henry Cook
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f9b85d8158
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NetworkIOs no longer use thunks
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2013-09-10 16:15:19 -07:00 |
|
Henry Cook
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d06e24ac24
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new enum syntax
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2013-09-10 10:51:35 -07:00 |
|
Henry Cook
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
|
Henry Cook
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
|
Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
|
Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
|
Henry Cook
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bef6c1db35
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minor nbdcache cleanup
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2013-08-02 16:29:37 -07:00 |
|
Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
|
Henry Cook
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569d8fd796
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Merge branch 'tilelink-data'
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2013-05-23 14:14:40 -07:00 |
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Henry Cook
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69b508ff39
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ported caches and htif to use new tilelink
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2013-05-21 17:21:04 -07:00 |
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Andrew Waterman
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1dab984231
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use UFix instead of Bits for arithmetic
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2013-05-18 00:45:29 -07:00 |
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Andrew Waterman
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474d321cc7
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fix meta hazard counter to reset on new meta writes
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2013-05-01 16:35:24 -07:00 |
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Andrew Waterman
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a6a88fce19
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Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
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2013-05-01 16:34:45 -07:00 |
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Andrew Waterman
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63a38e7982
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Revert "temp"
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
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2013-05-01 16:34:33 -07:00 |
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Henry Cook
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b6945408cb
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temp
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2013-05-01 10:24:36 -07:00 |
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Henry Cook
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722bc917d3
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broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
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2013-05-01 10:05:54 -07:00 |
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Andrew Waterman
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1501e90c1f
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interlock probe unit on tag RAW hazards
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2013-04-30 00:38:22 -07:00 |
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Henry Cook
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e8b20f3d38
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clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
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2013-04-25 17:41:04 -07:00 |
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Andrew Waterman
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ae7720e284
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guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
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2013-04-07 19:27:21 -07:00 |
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Andrew Waterman
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e74e032c87
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simplify MSHR memory response logic
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2013-04-06 01:03:37 -07:00 |
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Andrew Waterman
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1abb9277db
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fix LR/SC atomicity violation
note, it's still not starvation-free.
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2013-04-05 19:13:38 -07:00 |
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Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
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Henry Cook
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f8aebcbf8c
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fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
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2013-04-04 15:50:29 -07:00 |
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Henry Cook
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95f0a688e9
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Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
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Henry Cook
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273bd34091
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Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
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2013-03-20 15:53:36 -07:00 |
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Andrew Waterman
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ea9d0b771e
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remove aborts; simplify probes
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2013-03-19 15:29:40 -07:00 |
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Henry Cook
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e0361840bd
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writebacks on release network pass asm tests and bmarks
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2013-02-28 18:11:40 -08:00 |
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Andrew Waterman
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35349d227f
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update to new Mem style
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2013-02-20 16:09:46 -08:00 |
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Andrew Waterman
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1fbc20450e
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don't allow simultaneous reads and writes to the tag ram
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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37ee843b2c
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don't use reset combinationally
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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bb6fbddf1f
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don't probe the mshr file to inquire about refills
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2013-01-24 17:54:59 -08:00 |
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Rimas Avizienis
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63060bc0a8
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
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2013-01-23 19:27:53 -08:00 |
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Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
|
Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Henry Cook
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261e14f831
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Refactored uncore conf
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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f5c53ce35d
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add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
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2012-12-11 15:58:53 -08:00 |
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Andrew Waterman
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3f59e439ef
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fix d$ tag raw hazard
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2012-12-07 15:14:20 -08:00 |
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Andrew Waterman
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4dda38204f
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fix d$ reset bug
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2012-12-06 03:13:22 -08:00 |
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Andrew Waterman
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290d3d226c
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fix AMO and store bypass bugs
thanks, torture tester
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2012-12-06 02:07:52 -08:00 |
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Andrew Waterman
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4608660f6e
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torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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Andrew Waterman
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90cae54ac4
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fix D$ read/write concurrency bug
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2012-11-27 02:42:27 -08:00 |
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Andrew Waterman
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608f65e716
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don't wastefully read 2x the bits from D$ RAMs
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2012-11-26 20:34:30 -08:00 |
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Andrew Waterman
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8a6ff5f9aa
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fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
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2012-11-25 19:46:48 -08:00 |
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Andrew Waterman
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de2f28193a
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get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
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Andrew Waterman
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c036cdc1ea
|
add option for 2-cycle load-use delay
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2012-11-24 22:01:08 -08:00 |
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Andrew Waterman
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2b26082132
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use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
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2012-11-20 04:09:26 -08:00 |
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Andrew Waterman
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30038bda8a
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bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
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2012-11-20 01:33:32 -08:00 |
|
Yunsup Lee
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395e4e3dd6
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andrew'x fix for D$ corner case in writeback->abort->probe
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2012-11-18 03:11:06 -08:00 |
|
Yunsup Lee
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81d711e892
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fix D$ bug; now D$ doesn't respond to prefetches
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2012-11-17 20:06:13 -08:00 |
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Andrew Waterman
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29bc361d6c
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remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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Andrew Waterman
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e68b039133
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fix misc. D$ control bugs
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2012-11-17 06:47:27 -08:00 |
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Andrew Waterman
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dad7b71062
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provide cmd/addr with cache response
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2012-11-16 21:26:12 -08:00 |
|
Andrew Waterman
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cb8ac73045
|
provide store data with cache response
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2012-11-16 21:15:13 -08:00 |
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Andrew Waterman
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9e010beffe
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fix D$ refill bug
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2012-11-16 21:05:29 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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6d10115b19
|
fix D$ tag width
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2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
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9a02298f6f
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andrew's fix for tlb lockup
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2012-11-06 23:52:58 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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c5b93798fb
|
factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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Henry Cook
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88ac5af181
|
Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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Andrew Waterman
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fc648d13a1
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remove old Mux1H; add implicit conversions
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2012-10-16 02:24:37 -07:00 |
|
Henry Cook
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8970b635b2
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improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
|
Henry Cook
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9025d0610c
|
first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
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Andrew Waterman
|
ed8cc4a1cf
|
eliminate D$ probe->WB critical path
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2012-10-04 09:05:14 -07:00 |
|
Huy Vo
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e909093f37
|
factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
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Henry Cook
|
b9a9664de5
|
uncore and rocket changes for new xact types
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2012-10-01 10:47:36 -07:00 |
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Andrew Waterman
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0f20771664
|
rename queue to Queue
fixes build with case-insensitive file system
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2012-08-08 22:11:59 -07:00 |
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Andrew Waterman
|
938effc053
|
don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
|
Yunsup Lee
|
f633a55722
|
fix dcache tag array size
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2012-07-16 22:19:03 -07:00 |
|
Huy Vo
|
fd95159837
|
INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Andrew Waterman
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bac82762d3
|
use only one (wide) tag ram for set assoc. caches
|
2012-07-12 14:50:12 -07:00 |
|
Andrew Waterman
|
4e5f874266
|
update to new chisel/hwacha
|
2012-06-08 00:13:14 -07:00 |
|
Huy Vo
|
a99cebb483
|
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
|
2012-06-06 18:22:56 -07:00 |
|
Huy Vo
|
04304fe788
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Andrew Waterman
|
7f6319047e
|
update to new scala/chisel/Mem
|
2012-06-06 02:47:22 -07:00 |
|
Huy Vo
|
7408c9ab69
|
removing wires
|
2012-05-24 10:42:39 -07:00 |
|
Henry Cook
|
87cbae2c8a
|
Removed defunct ioDmem
|
2012-05-07 17:31:39 -07:00 |
|
Henry Cook
|
622a801bb1
|
Refactored cpu/cache interface to use nested bundles
|
2012-05-02 11:54:28 -07:00 |
|
Andrew Waterman
|
c13d3e6f88
|
fix probe tag read-modify-write atomicity violation
|
2012-04-26 02:29:31 -07:00 |
|
Henry Cook
|
1ed89f1cab
|
Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
|
2012-04-24 17:17:42 -07:00 |
|
Henry Cook
|
a39080d0b1
|
Fixed abort bug: xact_abort.ready was not pinned high
|
2012-04-24 17:16:40 -07:00 |
|
Andrew Waterman
|
fb4408b150
|
fix AMO replay/coherence deadlock
|
2012-04-15 22:56:02 -07:00 |
|
Andrew Waterman
|
724735f13f
|
fix writeback bug
|
2012-04-13 03:16:48 -07:00 |
|
Andrew Waterman
|
00d934cfac
|
fix coherence bugs in cache
|
2012-04-12 21:57:37 -07:00 |
|
Andrew Waterman
|
c0ec3794bf
|
coherence mostly works now
|
2012-04-10 02:22:45 -07:00 |
|
Henry Cook
|
3cdd166153
|
Refactored coherence as member rather than trait. MI and MEI protocols.
|
2012-04-10 00:09:58 -07:00 |
|
Henry Cook
|
0b4937f70f
|
changed coherence message type names
|
2012-04-09 23:29:31 -07:00 |
|
Henry Cook
|
ed79ec98f7
|
Refactored coherence better from uncore hub, better coherence function names
|
2012-04-09 23:29:31 -07:00 |
|
Yunsup Lee
|
1cddd5de56
|
fix amo locking up problem
|
2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
|
264732556f
|
fixes to match verilog X semantics
|
2012-03-19 03:10:00 -07:00 |
|
Andrew Waterman
|
cfca2d1411
|
clean up cache interfaces; avoid reserved keywords
|
2012-03-16 00:44:16 -07:00 |
|
Andrew Waterman
|
820884c7e6
|
fix probes for smaller cache sizes
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
|
2012-03-15 23:08:30 -07:00 |
|
Andrew Waterman
|
4684171ac6
|
fix fence.i for associative caches
|
2012-03-15 21:23:21 -07:00 |
|
Andrew Waterman
|
7dde7099d2
|
use broadcast hub and coherent HTIF
|
2012-03-14 16:44:35 -07:00 |
|
Andrew Waterman
|
1492457df5
|
add probe replies to HTIF
|
2012-03-13 16:56:47 -07:00 |
|
Andrew Waterman
|
b0f798962c
|
add probe unit
|
2012-03-13 16:43:51 -07:00 |
|
Henry Cook
|
287bc1c262
|
Further refinement of tag_match/tag_hit signals
|
2012-03-13 11:48:12 -07:00 |
|
Andrew Waterman
|
d76b05bde1
|
fix way selection on D$ write upgrades
|
2012-03-13 02:21:02 -07:00 |
|