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Author SHA1 Message Date
Andrew Waterman ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Andrew Waterman 2d1d7266f5 Fix RV64 badaddr value on instruction faults with large addresses 
We were relying on ALU passthrough for this, but failed to override the
ALU dw argument, so bits above 31 could be discarded.
 2016-08-15 23:09:09 -07:00
Andrew Waterman 2906c75167 Remove fsim, as it is the same as vsim, modulo CONFIG 2016-08-09 15:42:22 -07:00
Andrew Waterman 1b8f919db2 Remove unused CoreName parameter 2016-08-09 15:24:59 -07:00
Andrew Waterman 458520c8f6 Use a generic UInt for TileLink op sizes, rather than MT_xx enum 2016-08-09 15:24:51 -07:00
Andrew Waterman a857b08c59 [rocket] compute D$ tag bits based upon # of arbiter ports 2016-08-09 14:40:48 -07:00
Andrew Waterman cc0f8962fb [rocket] take physical memory attribute check off critical path 
Cache the attributes in the TLB instead.
 2016-08-02 17:21:03 -07:00
Andrew Waterman 76f33d88a6 [rocket] Respect physical memory protection during page table walks 2016-08-02 17:20:49 -07:00
Andrew Waterman 5d4f6383f2 [rocket] Automatically kill D$ access on address exceptions 
Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
 2016-08-02 17:20:49 -07:00
Andrew Waterman b54db0ba23 [rocket] don't update BTB on not-taken branches 
Only update the BHT; don't set the target prediction to pc+4.
 2016-08-02 17:20:49 -07:00
Andrew Waterman 64bde1060c [rocket] remove unused code in ibuf 2016-08-02 15:26:09 -07:00
Andrew Waterman 2ce702dc0a [rocket] fix PTW critical path 
Pipeline the killing of a D$ request following a PTW cache hit.
 2016-08-02 15:19:48 -07:00
Andrew Waterman 7e9d139e49 [rocket] remove rocket-specific require() from HasCoreParameters 2016-08-02 15:19:48 -07:00
Andrew Waterman 791a27748b Update firrtl and remove firrtl hack in plic 2016-08-02 15:19:48 -07:00
Andrew Waterman fe670e5421 Stop using deprecated FileSystemUtilities to create files 2016-07-31 18:04:56 -07:00
Andrew Waterman 832e56d3c7 Fix toBits/toUInt/toSInt deprecation warnings 2016-07-31 17:13:52 -07:00
Andrew Waterman a6e009d8de [rocket] Fix frontend mask when fetchWidth == 1 2016-07-31 15:21:17 -07:00
Andrew Waterman c49dad2e9d Improve PTW QoR 2016-07-29 17:56:42 -07:00
Andrew Waterman cc635c386f Make Chisel3 the default version for SBT 2016-07-29 17:56:42 -07:00
Andrew Waterman 058396aefe [rocket] Implement RVC 2016-07-29 17:56:42 -07:00
Andrew Waterman c465120610 [rocket] use more standard pattern for computing integer min 2016-07-29 17:56:42 -07:00
Andrew Waterman ffac86b041 [rocket] only write badaddr on certain exceptions 2016-07-29 17:56:42 -07:00
Andrew Waterman 0d3d9fca25 [rocket] Allow zapping of BTB entries 
This is necessary to guarantee forward progress with RVC, since if the
BTB keeps mispredicting, the processor might never successfully
fetch both halves of a misaligned instruction.
 2016-07-29 17:56:42 -07:00
Andrew Waterman 8e0392f24b [rocket] don't hard-code instruction width in BHT 2016-07-29 17:56:42 -07:00
Andrew Waterman 7cf44f9b25 clean up WideCounter implementation 2016-07-15 00:51:01 -07:00
Andrew Waterman ba08255450 bump rocket 2016-07-14 22:11:19 -07:00
Andrew Waterman d78f1aacd0 Clean up some zero-width wire cases using UInt.extract 2016-07-14 22:08:01 -07:00
Andrew Waterman da512d4230 Explicitly discard BTB index LSBs 2016-07-14 17:10:27 -07:00
Andrew Waterman 768403f8fa Bump rocket; remove ICacheBufferWays parameter 2016-07-14 12:50:16 -07:00
Andrew Waterman e6aab368a4 Replace ICacheBufferWays parameter with I$ constructor argument 2016-07-14 12:38:54 -07:00
Andrew Waterman 3d0b92afd7 Misc code cleanup 2016-07-14 12:09:34 -07:00
Andrew Waterman b8884e8143 Simplify frontend virtual address extension code 2016-07-14 12:05:09 -07:00
Andrew Waterman 1699622730 Don't speculatively refill I$ in uncacheable regions 2016-07-09 01:10:58 -07:00
Andrew Waterman 32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Andrew Waterman 3d8939d3c3 Set misa.base = 1 for RV32 2016-07-07 15:32:21 -07:00
Andrew Waterman 2455a806af Make WFI instruction respect mie CSR setting 2016-07-07 15:31:17 -07:00
Andrew Waterman 35a983275e Guarantee one-hotness of BTB entries 2016-07-06 15:58:01 -07:00
Andrew Waterman 2a146155fc Update to new priv-1.9 PTE format 2016-07-06 10:15:59 -07:00
Andrew Waterman 8625f9ea0c Update PTE format 2016-07-06 03:20:41 -07:00
Andrew Waterman c0e6ecebfc Fix BTB perf bug 
In rare cases, it would replace into a different row than it recorded.
 2016-07-06 03:16:05 -07:00
Andrew Waterman f3e22984d5 Remove uarch counters 
These will be replaced with the indirect TDR scheme used by breakpoints.
 2016-07-06 01:41:41 -07:00
Andrew Waterman 25fdabdd59 Don't implicitly create Vecs, since they're heavyweight 2016-07-06 01:41:31 -07:00
Andrew Waterman 8bd7e3932b Implement priv-1.9 PTE scheme 2016-07-05 19:19:49 -07:00
Andrew Waterman ebefe57036 simplify BTB fetchWidth=1 special case 2016-07-04 23:43:47 -07:00
Andrew Waterman 85808f8cbb Clean up PseudoLRU code 2016-07-02 15:09:12 -07:00
Andrew Waterman 2d325df60c Improve PTW simulation performance 2016-07-02 14:34:18 -07:00
Andrew Waterman 5aa8ef1855 Remove invalidation support from BTB 
Validating the target PC in the pipeline is cheaper than maintaining
the valid bits and control logic to guarantee the BTB won't ever
mispredict branch targets.
 2016-07-02 14:27:29 -07:00
Andrew Waterman 663002ec0c Improve TLB simulation performance 2016-07-02 14:26:05 -07:00
Andrew WatermanandHoward Mao f1cbb2ff77 Turn up optimization for Verilator compilation 2016-06-28 14:12:46 -07:00
Andrew Waterman c10691b616 Don't take interrupts on instructions in branch shadow 
In situations like

       j 1f
       nop
    1: nop

the interrupt could be taken on the first nop.
 2016-06-28 12:47:49 -07:00
Andrew Waterman a70dee17ea Make RoCC energy-saving logic mirror same for D$ 2016-06-28 12:47:45 -07:00
Andrew Waterman c725a78086 Merge RTC into PRCI 2016-06-27 23:08:29 -07:00
Andrew Waterman 97e74aec3a Merge RTC and PRCI 2016-06-27 23:06:07 -07:00
Andrew Waterman 87a4858aa6 Exit from testbench, not C code 
Otherwise, we don't get coverage data from the simulator.
 2016-06-23 20:54:07 -07:00
Andrew Waterman 568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Andrew Waterman 6fb07b1b79 Remove legacy HTIF things 2016-06-23 13:19:31 -07:00
Andrew Waterman 6f85056494 Remove reliance on HtifKey 2016-06-23 13:18:51 -07:00
Andrew Waterman 354b81c8fe Remove legacy HTIF things 
The SCR file is gone, too, because it is tightly coupled.  The
general concept could be revived as a module that somehow connects
to (or is contained by) the debug module.
 2016-06-23 13:17:11 -07:00
Andrew Waterman 2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman 1844bac5bc Use stop() to exit cleanly 2016-06-23 12:16:37 -07:00
Andrew Waterman 30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Andrew Waterman f57524e0c1 Remove FENCE.I from debug ROM; specialize for RV64 2016-06-23 00:01:26 -07:00
Andrew Waterman 6d43c0a945 Mask interrupts during single-step 2016-06-23 00:01:06 -07:00
Andrew Waterman 5644a2703a Avoid need for FENCE.I in debug programs 
This is a hack to work around caching the (uncacheable) debug RAM.  The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
 2016-06-23 00:01:06 -07:00
Andrew Waterman 7f88a00a38 Always verify BTB result; don't bother flushing it 
This improves CPI for things like

    lbu t0, (t0)
    j foo
    addi t0, t0, 1

where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
 2016-06-23 00:01:06 -07:00
Andrew Waterman 4a8e6c773a Fix +verbose flag for verilator 2016-06-17 21:09:08 -07:00
Andrew Waterman 60bddddfe6 Merge sptbr and sasid 2016-06-17 18:29:05 -07:00
Andrew Waterman 0b4c8e9af7 Add D-mode single-step support 2016-06-15 16:21:24 -07:00
Andrew Waterman e3b4b55836 Refactor breakpoints and support range comparison (currently disabled) 2016-06-10 19:55:58 -07:00
Andrew Waterman b79db89c03 Update breakpoint spec 2016-06-09 19:13:55 -07:00
Andrew Waterman c8c7246cce Update breakpoint spec 2016-06-09 19:07:21 -07:00
Andrew Waterman 586c1079d0 Fix D$ for set size > page size 2016-06-09 13:02:28 -07:00
Andrew Waterman dca55a2b35 Respect breakpoint privilege settings 2016-06-09 12:41:52 -07:00
Andrew Waterman c85ea7b987 Set badaddr on breakpoints 2016-06-09 12:33:43 -07:00
Andrew Waterman 4cd77cef10 Make dcsr.halt writable 2016-06-09 12:30:09 -07:00
Andrew Waterman 9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Andrew Waterman e3c17b5f74 Add provisional breakpoint support 2016-06-08 20:19:52 -07:00
Andrew Waterman 2c17f828b6 bump chisel and rocket 2016-06-06 21:36:51 -07:00
Andrew Waterman 4f2e2480a8 When exceptions occur in D-mode, set pc=0x808, not 0x800 
Closes #43
 2016-06-06 20:57:22 -07:00
Andrew Waterman dd85f2410f Avoid need for cloneType 2016-06-05 23:47:56 -07:00
Andrew Waterman 631e3e2dd9 Make PRCI a singleton, not per-tile 
Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
 2016-06-05 23:06:21 -07:00
Andrew Waterman be7500e4a9 Update PLIC addr map 2016-06-05 23:04:51 -07:00
Andrew Waterman 3b0c1ed0c3 Cope with changes to AddrMap 2016-06-03 13:50:29 -07:00
Andrew Waterman cf8be98b2b Cope with changes to AddrMap 2016-06-03 13:48:43 -07:00
Andrew Waterman 2e88ffc364 Cope with changes to AddrMap 2016-06-03 13:48:09 -07:00
Andrew Waterman 28161cab45 Merge AddrHashMap and AddrMap 2016-06-03 13:46:53 -07:00
Andrew Waterman f1745bf142 Allow PLIC nPriorities=0 (priority fixed at 1) 2016-06-02 13:48:29 -07:00
Andrew Waterman b7ca2145b3 Fix PLIC control bug when !grant.ready 2016-06-02 13:47:59 -07:00
Andrew Waterman 0866b4c045 Can't assign to Vec literals 2016-06-01 23:36:34 -07:00
Andrew Waterman 20e1de08da Avoid chisel2 pitfall 
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3.  D'oh.
 2016-06-01 23:35:49 -07:00
Andrew Waterman 5629fb62bf Avoid bitwise sub-assignment 2016-06-01 21:59:02 -07:00
Andrew Waterman 9518b3d589 Fix arithmetic in ROM row count 2016-06-01 21:59:02 -07:00
Andrew Waterman 8e80d1ec80 Avoid floating-point arithmetic where integers suffice 2016-06-01 21:59:02 -07:00
Andrew Waterman 13386af1d1 Get rid of unused implicit conversion 2016-06-01 19:30:41 -07:00
Andrew Waterman 9949347569 First stab at debug interrupts 2016-06-01 16:57:10 -07:00
Andrew Waterman 1311e78d3f Add blocking D$ flush support 2016-05-31 19:28:41 -07:00
Andrew Waterman 51379621d6 Flush blocking D$ on FENCE.I 2016-05-31 19:27:28 -07:00
Andrew Waterman 6d82c0d156 Add M_FLUSH_ALL command 2016-05-31 19:25:31 -07:00
Andrew Waterman 44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman 56897f707a Don't rely on Mux1H output when no inputs are hot 2016-05-27 13:38:01 -07:00