riscv/rocket-chip
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Make WFI instruction respect mie CSR setting

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This commit is contained in:
Andrew Waterman 2016-07-07 15:30:43 -07:00
parent 35a983275e
commit 2455a806af
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/csr.scala
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@ -367,7 +367,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
insn_call || insn_break
when (insn_wfi) { reg_wfi := true }
when (read_mip.orR) { reg_wfi := false }
when (pending_interrupts.orR) { reg_wfi := false }
val cause =
Mux(!io.csr_xcpt, io.cause,