riscv/rocket-chip
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Update PTE format

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This commit is contained in:
Andrew Waterman
2016-07-06 03:20:41 -07:00
parent ee624b1c6e
commit 8625f9ea0c
1 changed files with 6 additions and 2 deletions
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8
groundtest/src/main/scala/tile.scala
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@@ -51,8 +51,12 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
s2_resp.pte.ppn := s2_ppn
s2_resp.pte.reserved_for_software := UInt(0)
s2_resp.pte.d := Bool(true)
s2_resp.pte.r := Bool(false)
s2_resp.pte.typ := UInt("b0101")
s2_resp.pte.a := Bool(false)
s2_resp.pte.g := Bool(false)
s2_resp.pte.u := Bool(true)
s2_resp.pte.r := Bool(true)
s2_resp.pte.w := Bool(true)
s2_resp.pte.x := Bool(false)
s2_resp.pte.v := Bool(true)
io.requestors.zipWithIndex.foreach { case (requestor, i) =>