[rocket] don't hard-code instruction width in BHT
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@ -62,11 +62,11 @@ class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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// - each counter corresponds with the address of the fetch packet ("fetch pc").
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// - updated when a branch resolves (and BTB was a hit for that branch).
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// The updating branch must provide its "fetch pc".
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class BHT(nbht: Int)(implicit p: Parameters) {
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class BHT(nbht: Int)(implicit val p: Parameters) extends HasCoreParameters {
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val nbhtbits = log2Up(nbht)
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def get(addr: UInt, update: Bool): BHTResp = {
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val res = Wire(new BHTResp)
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val index = addr(nbhtbits+1,2) ^ history
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val index = addr(nbhtbits+1, log2Up(coreInstBytes)) ^ history
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res.value := table(index)
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res.history := history
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val taken = res.value(0)
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@ -74,7 +74,7 @@ class BHT(nbht: Int)(implicit p: Parameters) {
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res
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}
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def update(addr: UInt, d: BHTResp, taken: Bool, mispredict: Bool): Unit = {
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val index = addr(nbhtbits+1,2) ^ d.history
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val index = addr(nbhtbits+1, log2Up(coreInstBytes)) ^ d.history
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table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
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}
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