riscv/rocket-chip
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Fix BTB perf bug

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In rare cases, it would replace into a different row than it recorded.
This commit is contained in:
Andrew Waterman 2016-07-06 03:16:05 -07:00
parent f3e22984d5
commit c0e6ecebfc
1 changed files with 2 additions and 3 deletions
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5
rocket/src/main/scala/btb.scala
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@ -182,9 +182,8 @@ class BTB(implicit p: Parameters) extends BtbModule {
val useUpdatePageHit = updatePageHit.orR
val usePageHit = pageHit.orR
val doIdxPageRepl = !useUpdatePageHit
val idxPageRepl = UIntToOH(nextPageRepl)
val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit,
Mux(usePageHit, Cat(pageHit(nPages-2,0), pageHit(nPages-1)), idxPageRepl))
val idxPageRepl = Mux(usePageHit, Cat(pageHit(nPages-2,0), pageHit(nPages-1)), UIntToOH(nextPageRepl))
val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
val idxPageUpdate = OHToUInt(idxPageUpdateOH)
val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))