Remove uarch counters
These will be replaced with the indirect TDR scheme used by breakpoints.
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parent
25fdabdd59
commit
f3e22984d5
@ -121,7 +121,6 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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val evec = UInt(OUTPUT, vaddrBitsExtended)
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val exception = Bool(INPUT)
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val retire = UInt(INPUT, log2Up(1+retireWidth))
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val uarch_counters = Vec(16, UInt(INPUT, log2Up(1+retireWidth)))
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val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen))
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val cause = UInt(INPUT, xLen)
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val pc = UInt(INPUT, vaddrBitsExtended)
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@ -207,7 +206,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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val reg_sptbr = Reg(new PTBR)
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val reg_wfi = Reg(init=Bool(false))
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val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
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val reg_fflags = Reg(UInt(width = 5))
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val reg_frm = Reg(UInt(width = 3))
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@ -474,7 +474,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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csr.io.rocc.interrupt <> io.rocc.interrupt
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csr.io.pc := wb_reg_pc
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csr.io.badaddr := Mux(wb_reg_mem_xcpt, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), wb_reg_pc)
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csr.io.uarch_counters.foreach(_ := Bool(false))
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io.ptw.ptbr := csr.io.ptbr
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io.ptw.invalidate := csr.io.fatc
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io.ptw.status := csr.io.status
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