[rocket] Respect physical memory protection during page table walks
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5d4f6383f2
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@ -72,8 +72,8 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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}
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require(usingAtomics, "PTW requires atomic memory operations")
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val s_ready :: s_req :: s_wait :: s_set_dirty :: s_wait_dirty :: s_done :: Nil = Enum(UInt(), 6)
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val s_ready :: s_req :: s_wait1 :: s_wait2 :: s_set_dirty :: s_wait1_dirty :: s_wait2_dirty :: s_done :: Nil = Enum(UInt(), 8)
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val state = Reg(init=s_ready)
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val count = Reg(UInt(width = log2Up(pgLevels)))
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val s1_kill = Reg(next = Bool(false))
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@ -96,7 +96,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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when ((tmp.ppn >> ppnBits) =/= 0) { res.v := false }
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res
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}
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val pte_addr = Cat(r_pte.ppn, vpn_idx) << log2Up(xLen/8)
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val pte_addr = Cat(r_pte.ppn, vpn_idx) << log2Ceil(xLen/8)
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when (arb.io.out.fire()) {
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r_req := arb.io.out.bits
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@ -132,7 +132,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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io.mem.req.valid := state === s_req || state === s_set_dirty
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io.mem.req.bits.phys := Bool(true)
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io.mem.req.bits.cmd := Mux(state === s_set_dirty, M_XA_OR, M_XRD)
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.typ := log2Ceil(xLen/8)
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io.mem.req.bits.addr := pte_addr
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io.mem.s1_data := pte_wdata.asUInt
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io.mem.s1_kill := s1_kill
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@ -163,10 +163,17 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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count := count + 1
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r_pte.ppn := pte_cache_data
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}.elsewhen (io.mem.req.ready) {
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state := s_wait
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state := s_wait1
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}
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}
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is (s_wait) {
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is (s_wait1) {
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state := s_wait2
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when (io.mem.xcpt.pf.ld) {
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r_pte.v := false
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state := s_done
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}
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}
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is (s_wait2) {
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when (io.mem.s2_nack) {
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state := s_req
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}
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@ -185,10 +192,17 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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}
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is (s_set_dirty) {
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when (io.mem.req.ready) {
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state := s_wait_dirty
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state := s_wait1_dirty
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}
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}
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is (s_wait_dirty) {
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is (s_wait1_dirty) {
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state := s_wait2_dirty
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when (io.mem.xcpt.pf.st) {
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r_pte.v := false
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state := s_done
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}
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}
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is (s_wait2_dirty) {
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when (io.mem.s2_nack) {
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state := s_set_dirty
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}
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