Megan Wachs
44edc5fdc3
test_mode_reset: Use simpler apply() method
2017-09-14 13:16:13 -07:00
Megan Wachs
82c00cb656
reset_catch: Allow Test Mode Overrides
2017-09-14 13:16:13 -07:00
Henry Cook
e50d14415e
tilelink: more verbose requires
2017-09-13 11:25:42 -07:00
Henry Cook
56dae946b6
coreplex: MemoryBusParams.beatBytes also based on XLen
2017-09-13 11:25:42 -07:00
Henry Cook
b86f4b9bb7
config: use Field defaults over Config defaults
...
Also rename some keys that had the same class name as their value's class name.
2017-09-13 11:25:42 -07:00
Henry Cook
a7540d35b7
ports: use BigInts instead of Longs and the new x"..." context
2017-09-13 11:25:42 -07:00
Henry Cook
37c5af1c0d
diplomacy: add x"..." string context
...
Enables hex address literals containing underscores.
Converts them to BigInts.
2017-09-13 11:25:42 -07:00
Henry Cook
063ca0ed4a
Merge pull request #983 from freechipsproject/kill-paddrbits
...
Remove global fields PAddrBits and ResetVectorBits
2017-09-11 12:51:10 -07:00
Andrew Waterman
1f606d924f
Don't perform in-place correction if there was a recent store ( #988 )
...
Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store. So,
re-read the word after all pending stores have drained.
2017-09-08 16:26:54 -07:00
Henry Cook
9c0bfbd500
tile: remove global Field ResetVectorBits
...
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
2017-09-08 14:50:59 -07:00
Henry Cook
3133c321b7
scratchpad: remove dependency on HasCoreParameters
2017-09-08 13:55:40 -07:00
Henry Cook
e46aeb7342
tile: remove PAddrBits in favor of SharedMemoryTLEdge
2017-09-08 13:53:36 -07:00
Wesley W. Terpstra
e7de7f3e82
Merge pull request #985 from freechipsproject/flop-interrupts
...
Add Parameters to diplomatic edges
2017-09-08 13:16:11 -07:00
Andrew Waterman
53dfc5e9be
Remove overzealous assertion ( #987 )
...
This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled. However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.
This happens when resolving a tag ECC error during hit-under-miss.
2017-09-07 18:17:56 -07:00
Wesley W. Terpstra
e723a3f42b
MemoryBus: fanout the A for performance
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6879f5bfb1
tilelink: Xbar now allows for fanout control
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
e831acba9c
adapters: support bulk connections
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
06a244f9f9
diplomacy: rename {Left,Right}Star to refer to {Source,Sink}Cardinality
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
bef593c21a
diplomacy: edges now capture their Parameters
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80ed27683e
diplomacy: protect against API leakage
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1365c5f90c
diplomacy: implement DisableMonitors scope
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
a450357744
tilelink: Monitor construction method is unconditional
...
Whether or not a Monitor should be placed is decided by diplomacy.
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
7a8364ef08
diplomacy: leverage new Parameters defaults
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
655a08f12e
config: support default values for Field[T] keys
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
09d8d476c5
config: require Parameters keys to be Field[T]
...
This has been good practice for ages. Enforce it.
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
42f1ae27fc
Xbar: use the IdentityModule to encourage wider fanout
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
5626cdd18f
util: add the IdentityModule, useful to dedup wires
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1a87ed1193
coreplex: add externalSlaveBuffers configuration option
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910
coreplex: rename externalBuffers to externalMasterBuffers
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
4911a7d44f
tilelink Bus: toAsyncSlaves now supports BufferChains
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
040f7e1d49
tilelink: add Bus.toSyncSlaves for easy BufferChain attachment
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
d5c6494f59
tilelink: Bus.toRationalSlaves can have a BufferChain
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80965e8230
tilelink Buffer: use new :=? adapter API
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1b705f62f6
diplomacy: support :=? for unknown star inference
2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6bfea86dbf
config: support p.lift(key) to optionally return a value
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
2d93262f71
RationalCrossing: use ShiftQueues
...
These are faster and small don't cost much more.
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
50d5d8c1fd
ShiftQueue: added a helper object
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
3e3024c256
ShiftQueue: fix bug in !flow case
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
ed70b243bd
plic: support a configurable number of interrupt register stages
2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
9b55063de6
clint: support a configurable number of interrupt register stages
2017-09-07 16:03:34 -07:00
Megan Wachs
126d56b254
synchronizers: I learn how foldRight works
2017-09-07 10:48:27 -07:00
Megan Wachs
1da6cb85ab
shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.
2017-09-07 09:57:50 -07:00
Megan Wachs
dcafb5fea3
Merge remote-tracking branch 'origin/master' into async_reg
2017-09-06 11:07:19 -07:00
Megan Wachs
3c4b472f66
shift regs: remove some unnecessary primitives, and add some that actually are necessary
2017-09-06 10:37:59 -07:00
Jim Lawson
f1b7666d21
Jtagresettobool - add explicit toBool cast now required on reset. ( #984 )
...
Add explicit toBool cast on reset, for chisel3 compatability
2017-09-06 09:49:47 -07:00
Megan Wachs
777f052f95
regs: Add named/initial value ShiftRegister primitives so they are all in one place
2017-09-05 17:32:53 -07:00
Wesley W. Terpstra
b1cacc56ad
SystemBus: restore correct order of FIFOFixer and Buffer
2017-09-05 16:41:39 -07:00
Wesley W. Terpstra
b74a419bfb
FrontBus: FIFOFixer should not have a buffer between it and Xbar
2017-09-05 16:27:57 -07:00
Megan Wachs
e9e46db600
sync reg: Rename the file to reflect the more generic shift registers also in the file.
2017-09-05 15:54:25 -07:00
Megan Wachs
5df23c5514
Synchronizers: remove some newlines and unncessary gen's
2017-09-05 15:17:21 -07:00
Wesley W. Terpstra
e65f49b89a
FrontBus: attach to splitter for cross-chip visibility
2017-09-05 15:03:41 -07:00
Wesley W. Terpstra
5886025b1a
sbus => pbus: 2 buffers should already be enough
...
There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.
Between them is only an AtomicAutomata.
That should be enough for most designs.
2017-09-05 15:03:38 -07:00
Henry Cook
a902e15987
pbus: clarify that we are adding buffers when attaching to sbus
2017-09-05 15:03:38 -07:00
Henry Cook
8fc4d78c84
frontbus: provide fifofixer on the side of the front bus where masters connect
2017-09-05 15:03:38 -07:00
Megan Wachs
667d966410
TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming
2017-09-05 15:03:38 -07:00
Megan Wachs
94f06dc85c
pbus: turn down overkill buffering between PBus and SBus
2017-09-05 15:03:38 -07:00
Megan Wachs
c353f68dc0
buses: name dummy buffers too
2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6
coreplex: allow buffer chains on certain bus ports
2017-09-05 15:03:36 -07:00
Megan Wachs
57d0360c35
frontbus: Name the connection.
2017-08-30 18:07:34 -07:00
Megan Wachs
c99afe4c66
buses: Name all the things.
2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81
coreplex: include optional tile name for downstream name stabilization
2017-08-30 15:48:55 -07:00
Megan Wachs
183fefb2b9
Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in
2017-08-30 15:27:56 -07:00
Wesley W. Terpstra
d5b62dffda
SystemBus: add stupidly many (4 more) buffers from sbus=>pbus
...
This should probably be reverted.
2017-08-30 14:22:49 -07:00
Henry Styles
f7330028cc
Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter
2017-08-30 14:22:49 -07:00
Wesley W. Terpstra
173f185b17
Merge pull request #976 from freechipsproject/system-buffer
...
SystemBus: add output buffering
2017-08-30 23:22:13 +02:00
Wesley W. Terpstra
656609d610
SystemBus: split FIFOFixers along bus boundaries
...
If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
2017-08-30 13:28:11 -07:00
Megan Wachs
a3bc5f2e33
synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive
2017-08-30 12:59:16 -07:00
Megan Wachs
8139014c9e
syncrhonizers: Remove unused sync from superclass
2017-08-30 12:33:03 -07:00
Megan Wachs
9dd6c4c32d
synchronizers: New chisel ways of cloning type and use simpler lambda function
2017-08-30 12:11:14 -07:00
Megan Wachs
bd32f0c122
synchronizers: properly pass parameters up to the superclass
2017-08-30 11:58:25 -07:00
Megan Wachs
483e63da19
synchronizers: Correctly pass the width through
2017-08-30 11:50:25 -07:00
Megan Wachs
a62ce0afe6
TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer.
2017-08-29 10:36:46 -07:00
Megan Wachs
c473538e36
Merge remote-tracking branch 'origin/master' into async_reg
2017-08-28 17:19:03 -07:00
Megan Wachs
451334ac73
Add 1-deep synchronizer register for output of AsyncQueue
2017-08-28 17:18:54 -07:00
Wesley W. Terpstra
bf19440db5
SystemBus: use a full buffer on slaves
2017-08-26 02:47:04 -07:00
Megan Wachs
85c39b2f97
syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
2017-08-24 17:47:04 -07:00
Megan Wachs
4e773f4738
syncregs: Use synchronizer primivites for LevelSyncCrossing
2017-08-24 17:42:31 -07:00
Megan Wachs
130b24355f
syncregs: Use synchronizer primitives for IntXing
2017-08-24 17:39:07 -07:00
Megan Wachs
8b462d1595
syncregs: Use common primitives for AsyncQueue grey code synchronizers
2017-08-24 17:34:07 -07:00
Megan Wachs
3461cb47cc
syncregs: Make Reset catcher use the synchronizer primitive
2017-08-24 17:26:38 -07:00
Megan Wachs
c78ee9f0e4
syncreg: Refactor common code
2017-08-24 17:18:04 -07:00
Megan Wachs
d83a6dc6af
syncregs: Add utilities for Synchronizing Shift Registers
2017-08-24 16:55:17 -07:00
Megan Wachs
7f683eeb24
async_regs: Make modules have predictable names
2017-08-24 15:33:53 -07:00
Megan Wachs
0f75ebee92
async_reg: Rename the file to match scalastyle
2017-08-24 15:31:29 -07:00
Megan Wachs
103b6bc6d3
systemBus: allowing naming the TLBuffers which get inserted
2017-08-24 14:49:12 -07:00
Wesley W. Terpstra
17134125e1
SystemBus: remove misnamed functions ( #972 )
...
These functions were actually for cross connecting chips.
2017-08-24 23:35:01 +02:00
Andrew Waterman
82df766f4a
Merge pull request #963 from freechipsproject/interrupt-order
...
Respect ISA requirements on interrupt priority order
2017-08-18 00:10:19 -07:00
Andrew Waterman
8087a205cc
Remove redundant check in interrupt priority encoding
...
chooseInterrupts already sorts M interrupts above S interrupts.
2017-08-17 22:23:42 -07:00
Andrew Waterman
cbe7c51b50
Respect ISA requirements on interrupt priority order
...
a62e76cb16
2017-08-17 21:27:08 -07:00
Shreesha Srinath
b1719cfee0
Fixing requirements for PAddrBits ( #961 )
...
Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.
2017-08-17 11:53:59 -07:00
Megan Wachs
1db4b3be9a
Merge pull request #957 from freechipsproject/param_jtag_vpi
...
jtag_vpi: Use Parameterized Black Box
2017-08-14 18:37:30 -07:00
Megan Wachs
8783d51c97
jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed
2017-08-14 17:25:47 -07:00
Wesley W. Terpstra
710a782145
HeterogenousBag: empty bags were being combined! ( #956 )
...
This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
2017-08-14 15:48:42 -07:00
Andrew Waterman
e945f6e265
Merge pull request #955 from freechipsproject/fix-acquire-before-release
...
Fix acquire before release
2017-08-13 18:29:58 -07:00
Megan Wachs
88332bd885
max-core-cycles: Add a +max-core-cycles PlusArg
2017-08-13 15:47:14 -07:00
Andrew Waterman
3cbc5262ec
Don't permit new acquires until the release queue is drained
...
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
Andrew Waterman
0190724492
Actually use the C-channel acquire-before-release queue
...
oops...
2017-08-13 13:03:35 -07:00
Andrew Waterman
7387f2a93a
Don't block D-channel when handling a probe
...
This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
Andrew Waterman
604abd5b07
Only report ECC errors when the RAM was actually read
2017-08-12 15:28:03 -07:00
Andrew Waterman
18fb052fc9
DRY
2017-08-12 15:27:30 -07:00
Andrew Waterman
176110b6d3
Don't trigger ECC writebacks when a release is in flight
2017-08-12 15:23:57 -07:00
Wesley W. Terpstra
f191bb994c
PatternPusher: can now expect a certain output ( #952 )
2017-08-11 18:10:27 -07:00
Wesley W. Terpstra
baf769f924
tilelink: add PatternPusher, a device to inject a fixed traffic pattern ( #950 )
2017-08-11 15:07:10 -07:00
Andrew Waterman
a3358f34a0
Fix priority inversion for two back-to-back divides ( #948 )
...
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit. While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
2017-08-10 17:12:09 -07:00
Andrew Waterman
0a591c5b5b
Roll back use of UIntToOH1 ( #946 )
...
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass. This is not yet conclusive.
2017-08-09 18:39:47 -07:00
Andrew Waterman
721770244e
Fix IBuf bug
...
Don't examine a packet's xcpt signal if it might be invalid. In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
2017-08-09 09:47:51 -07:00
Wesley W. Terpstra
a9b1410f01
BusBlocker: parameterize page granularity
2017-08-08 17:10:01 -07:00
Wesley W. Terpstra
010ba94474
BusBlocker: rename a variable
2017-08-08 17:00:22 -07:00
Wesley W. Terpstra
6d6fc38787
BusBlocker: lock bit should affect the prior PMP address, not next
2017-08-08 17:00:12 -07:00
Andrew Waterman
809c7e8551
Don't merge stores that manifest WAW hazards
...
The following sequence would drop the first store when eccBytes=4:
sb x0, 0(t0)
nop
sb x0, 4(t0)
nop
sb x0, 1(t0)
Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
2017-08-08 15:19:05 -07:00
Wesley W. Terpstra
3ef6e4c9f2
Merge pull request #939 from freechipsproject/bus-blocker
...
tilelink: PMP controlled BusBlocker prevents bus accesses
2017-08-08 15:06:55 -07:00
Andrew Waterman
82e13443b2
Merge pull request #937 from freechipsproject/critical-paths
...
Perform tag error detectoin/correction in same cycle as RAM
2017-08-08 15:03:28 -07:00
Wesley W. Terpstra
8f261adc6b
BusBlocker: change default policy to deny
2017-08-08 14:19:59 -07:00
Wesley W. Terpstra
0d76e96b88
tilelink: PMP controlled BusBlocker prevents bus accesses
2017-08-08 13:28:01 -07:00
Andrew Waterman
7935c61c19
Don't report to the DTIM that data is cacheable
...
Otherwise, it will attempt to perform AMOs where they're unsupported!
2017-08-08 11:55:04 -07:00
Andrew Waterman
74d309c18e
Make I vs. D a static property of TLB, not an input pin
...
The microarchitecture doesn't really support unified TLBs, so don't fake it.
2017-08-08 11:54:47 -07:00
Andrew Waterman
e92981b0bd
DRY
2017-08-08 11:46:38 -07:00
Andrew Waterman
62ccba304c
Perform tag error detectoin/correction in same cycle as RAM
...
The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
2017-08-08 10:21:30 -07:00
Palmer Dabbelt
6d1d285464
Merge pull request #933 from freechipsproject/cinst
...
Print out the compressed instruction when executing one
2017-08-07 21:40:10 -07:00
Palmer Dabbelt
cc1e2af336
Merge pull request #934 from freechipsproject/critical-paths
...
Revert "Remove one gate from D$ ECC check"
2017-08-07 19:41:08 -07:00
Henry Cook
c8f8806df0
Merge pull request #932 from freechipsproject/tl-bus-delayer
...
tilelink: allow insertion of TLDelayer on TLBus outward node
2017-08-07 19:01:39 -07:00
Henry Cook
c4092dd0cc
tilelink: improve entropy of bus delayer
2017-08-07 17:36:07 -07:00
Andrew Waterman
402907990c
Revert "Remove one gate from D$ ECC check"
...
This reverts commit 7d94074b05
, which
works fine with optimistic behavioral RAMs but not real ones.
2017-08-07 17:33:20 -07:00
Henry Cook
2910d6fa2a
tilelink: make bus xbar protected so it can be suggestNamed
2017-08-07 17:30:24 -07:00
Palmer Dabbelt
fc0d5fcf98
Print out the compressed instruction when executing one
2017-08-07 17:21:53 -07:00
Wesley W. Terpstra
e27072e063
Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse
...
Fix ram model source reuse
2017-08-07 16:56:13 -07:00
Henry Cook
c457c9cb9f
tilelink: allow insertion of TLDelayer on TLBus outward node
2017-08-07 16:43:06 -07:00
Wesley W. Terpstra
f8b45564d1
tilelink: RAMModel must support source reuse
...
If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
2017-08-07 16:01:15 -07:00
Yunsup Lee
558fc7f293
maskrom: retain data for d channel is not ready
2017-08-07 12:17:10 -07:00
Andrew Waterman
7fd8bb1159
Merge pull request #928 from freechipsproject/critical-paths
...
Critical paths
2017-08-06 18:50:59 -07:00
Andrew Waterman
658e36f98b
Reduce fanout on frontend io.cpu.req.valid signal
2017-08-06 17:38:51 -07:00
Andrew Waterman
7d94074b05
Remove one gate from D$ ECC check
...
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
2017-08-06 17:36:53 -07:00
Wesley W. Terpstra
d03fdc4f30
diplomacy: seal the LazyModuleImpLike trait ( #927 )
...
This makes sure that all the base classes call instantiate()
2017-08-06 17:32:23 -07:00
Yunsup Lee
aa60c6944b
diplomacy: provide default clock/reset for LazyRawModuleImp
2017-08-06 13:40:07 -07:00
Andrew Waterman
83875e3a0c
Only flush D$ on FENCE.I if it won't always be probed on I$ miss
2017-08-05 14:22:40 -07:00
Andrew Waterman
991e16de92
Remove probe address mux from TLB response path
2017-08-05 12:57:38 -07:00
Andrew Waterman
b9b4142bb4
Get s2_nack off the critical path
...
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively). This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
2017-08-05 00:30:36 -07:00
Andrew Waterman
bc298bf146
Optimize ShiftQueue for late-arriving deq.ready
2017-08-04 22:06:37 -07:00
Andrew Waterman
6112adfbb0
Get L2 TLB tag/parity check off the D$ arbitration path
2017-08-04 17:01:51 -07:00
Andrew Waterman
8d97684555
Fix L2 TLB perfctr
...
It was counting conflict misses but not cold misses.
2017-08-04 17:01:31 -07:00
Andrew Waterman
df7f09b9ce
Get I$ ECC check further off critical path
2017-08-04 16:59:21 -07:00
Andrew Waterman
4bfbe75d74
Avoid pipeline replays when fetch queue is full
2017-08-04 16:59:21 -07:00
Andrew Waterman
a45997d03f
Separate I$ parity error from miss signal
...
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
2017-08-04 16:59:21 -07:00
Andrew Waterman
06a831310b
Shave a gate delay off I$ backpressure path
...
The deleted code was a holdover from Hwacha's vector fences.
2017-08-04 13:12:43 -07:00
Andrew Waterman
ecc2ee366c
Shave a few gate delays off IBuf control logic
...
It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
2017-08-04 13:12:43 -07:00
Andrew Waterman
7937db0c84
Merge pull request #919 from freechipsproject/imiss-perf-counter
...
Fix I$ miss perfctr
2017-08-04 01:04:23 -07:00
Megan Wachs
017ac130c1
Merge pull request #922 from freechipsproject/bigger_tl_xbar
...
TLXbar: Allow more masters and slaves and issue a warning.
2017-08-03 16:52:56 -07:00
Megan Wachs
50c85f1b62
TLXbar: Allow more masters and slaves and issue a warning.
2017-08-03 15:46:06 -07:00
Andrew Waterman
ba4eecc0f0
Use UIntToOH1 ( #921 )
...
Closes #920
2017-08-03 14:55:39 -07:00
Andrew Waterman
f483bab4aa
Fix I$ miss perfctr
...
The old version was counting prefetches, too.
2017-08-03 00:52:12 -07:00
Andrew Waterman
1be1433f04
Merge pull request #918 from freechipsproject/icache-prefetch
...
Icache prefetch
2017-08-02 21:22:20 -07:00
Andrew Waterman
d66e8f8e80
Merge pull request #914 from freechipsproject/critical-paths
...
Fix some critical paths
2017-08-02 19:05:31 -07:00
Megan Wachs
3fc7100048
Merge pull request #917 from freechipsproject/fuzzer_order
...
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 18:39:59 -07:00
Andrew Waterman
2537d0d54e
Optionally prefetch next I$ line into L2$ on miss
2017-08-02 17:10:56 -07:00
Andrew Waterman
744cdb2f72
Make TLB report when it's safe to prefetch within a page
2017-08-02 17:09:38 -07:00
Megan Wachs
595415d207
TLFuzzer: Correct the number of ordered clients created
2017-08-02 15:48:21 -07:00
Megan Wachs
fc5c04ed4b
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 14:44:18 -07:00
Andrew Waterman
7d2dd3769f
Optimize a hazard check critical path
2017-08-02 14:27:25 -07:00
Megan Wachs
85bdae0fa8
diplomacy: Pretty Print for TransferSizes
2017-08-02 11:40:50 -07:00
Andrew Waterman
2eb239d03f
Add option to retime D$ way mux into subsequent pipeline stage
2017-08-01 23:59:20 -07:00
Andrew Waterman
9464c6db40
Mitigate(?) frontend critical path
2017-08-01 18:51:17 -07:00
Andrew Waterman
735701382f
Mitigate some I$ response valid critical paths
2017-08-01 18:51:17 -07:00
Andrew Waterman
2ecea2ef60
Don't use a pipe queue on D$ TL A-channel
...
This cuts an I$->D$ path.
2017-08-01 15:17:07 -07:00
Yunsup Lee
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
Yunsup Lee
4b33249812
Merge pull request #911 from freechipsproject/fix-dcache-bug
...
Fix D$ ready-valid signaling bug
2017-07-31 19:14:16 -07:00
Wesley W. Terpstra
42ff74bd34
Merge pull request #910 from freechipsproject/tilelink-map
...
Tilelink map
2017-07-31 18:33:09 -07:00
Andrew Waterman
e140893a01
Use 1-entry queue on processor-side E-channel
...
The cache can't sink a grant every cycle, so extra E buffering doesn't help.
2017-07-31 18:06:54 -07:00
Andrew Waterman
5681693ccc
Fix a D$ ready-valid signaling regression
...
I broke this in 66d06460fa
.
2017-07-31 18:05:14 -07:00
Wesley W. Terpstra
d7fd9d2b82
tilelink: Filter, add another case
2017-07-31 16:51:26 -07:00
Yunsup Lee
71a250b071
Merge pull request #909 from freechipsproject/tile-buffer
...
add optional tile boundary buffers
2017-07-31 16:46:22 -07:00
Wesley W. Terpstra
b126105230
tilelink: add TLMap to make it possible to move slaves
2017-07-31 16:39:00 -07:00
Wesley W. Terpstra
13d3ffbcaa
tilelink: Filter now support arbitrary filter functions
2017-07-31 16:38:38 -07:00
Yunsup Lee
7adfd5c431
Merge pull request #906 from freechipsproject/critical-paths
...
Mitigate I$->D$->I$ critical path
2017-07-31 16:14:11 -07:00
Yunsup Lee
f473e6bad0
tile: add optional boundary buffers
2017-07-31 15:57:22 -07:00
Yunsup Lee
cb3529bbc3
util: tweak rational crossings to avoid mux in source
2017-07-31 15:10:15 -07:00
Henry Cook
11332c1226
dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative
2017-07-31 14:03:30 -07:00
Andrew Waterman
d811692c3b
Mitigate I$->D$->I$ critical path
...
This seemingly irrelevant change shaves several gate delays off the I$
tl.a.valid path.
2017-07-31 01:43:04 -07:00
Andrew Waterman
ac4339a8e7
Pass D$ backpressure to D-channel, rather than asserting
2017-07-29 11:48:36 -07:00
Andrew Waterman
edcd2c696c
Avoid needless stall on E-channel back pressure
2017-07-29 11:47:58 -07:00
Wesley W. Terpstra
8e2e931770
Merge pull request #903 from freechipsproject/monitor-probes
...
tilelink: use the Monitor to enforce Probe sourcing
2017-07-29 01:12:08 -07:00
Wesley W. Terpstra
56e28026a6
TLError: does not need to be fast; cut the loop
...
The SystemBus already has a flow buffer on outputs.
2017-07-29 00:22:21 -07:00
Wesley W. Terpstra
540256e24a
systembus: all slaves should have an output buffer
2017-07-29 00:13:33 -07:00
Wesley W. Terpstra
eadf4e9fcc
Revert "tile: add option for tile boundary buffers"
...
This reverts commit b64b87ad07
.
The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
2017-07-29 00:03:24 -07:00
Wesley W. Terpstra
68064ba260
systembus: don't double down on buffers
...
The order should be:
master => buffer|xing => fifofixer => splitter => xbar
2017-07-29 00:02:12 -07:00
Yunsup Lee
140086e2c5
Merge pull request #902 from freechipsproject/perf-improvements
...
Perf improvements
2017-07-28 20:12:10 -07:00
Wesley W. Terpstra
a0db929003
tilelink: use the Monitor to enforce Probe sourcing
2017-07-28 18:08:00 -07:00
Megan Wachs
573890e102
Merge pull request #900 from freechipsproject/more_verbose_requires
...
diplomacy: More verbose require
2017-07-28 13:23:33 -07:00
Andrew Waterman
fdb8935712
Improve fidelity of two perf counters
2017-07-28 13:14:04 -07:00
Andrew Waterman
4c82f6b77e
Don't refill BTB on not-taken branches
2017-07-28 13:13:52 -07:00
Andrew Waterman
2e8b02e780
Merge D$ store hits when ECC is enabled
...
This avoids pipeline flushes due to subword WAW hazards, as with
consecutive byte stores.
2017-07-28 12:56:36 -07:00
Andrew Waterman
838864870e
Bypass TLB refill signal to halve L2 TLB hit time
...
The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
2017-07-28 12:56:36 -07:00
Andrew Waterman
ae1f7a95f6
Don't nack misses when there's a pending store
...
That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss. Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
2017-07-28 12:56:36 -07:00
Henry Cook
7eeb9dfd88
Merge pull request #899 from freechipsproject/wrapper-dedup
...
Stabilize tile wrappers for downstream tools
2017-07-28 10:52:59 -07:00
Megan Wachs
f61fe2be1e
diplomacy: More verbose require
2017-07-28 10:05:45 -07:00
Wesley W. Terpstra
5f81c2243f
tilelink: add BusBypass, useful to turn devices off
2017-07-27 20:16:30 -07:00
Wesley W. Terpstra
9a36755b6a
tilelink: CacheCork uses constructor helpers
2017-07-27 18:38:15 -07:00
Wesley W. Terpstra
45189c3e30
tilelink: CacheCork now supports errors and BtoT upgrade
...
- Acquire.BtoT succeeds with toT instantly
- AccessAckData.error causes Grant.toN.error
2017-07-27 18:38:13 -07:00
Wesley W. Terpstra
2e4f1611ed
tilelink: Error device supports Acquire
...
We need this if we want to divert traffic to it from a TL-C slave.
2017-07-27 18:32:58 -07:00
Henry Cook
b64b87ad07
tile: add option for tile boundary buffers
2017-07-27 17:30:51 -07:00
Henry Cook
289ef30dbc
coreplex: change AsynchronousCrossing.sync default to 3
2017-07-27 15:44:51 -07:00
Henry Cook
266ed56e8d
tile: turn off more slave port monitors
2017-07-27 15:28:53 -07:00
Henry Cook
9a483af6e8
coreplex: naming of tile wrappers
2017-07-27 15:16:48 -07:00
Henry Cook
33852ef965
coreplex: remove superfluous sink and source from wrapper
2017-07-27 14:23:03 -07:00
Wesley W. Terpstra
651da73d89
tilelink: it is now legal to support Acquire for UNCACHED regions
...
These cases exist:
GET_EFFECTS, PUT_EFFECTS, UNCACHEABLE && !supportsAcquire: MMIO
UNCACHED && !supportsAcquire: speculation ok and may be cached
UNCACHED && supportsAcquire: LLC/CacheCork applied (slave never probes)
CACHED, TRACKED && supportsAcquire: slave might probe
2017-07-27 11:11:22 -07:00
Wesley W. Terpstra
0ab5cb67b3
tilelink: fix RAMModel handling of AMOs on early source reuse ( #897 )
2017-07-27 11:07:13 -07:00
Wesley W. Terpstra
9804bdc34e
tilelink: remove obsolete addr_lo signal ( #895 )
...
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
2017-07-26 16:01:21 -07:00
Wesley W. Terpstra
d096d5d1c4
tilelink: fix AtomicAutomata bug wrt early source reuse
...
The new fuzzer already found it's first victim.
2017-07-26 12:52:29 -07:00
Wesley W. Terpstra
6550ae2e31
tilelink: increase Fuzzer source reuse aggression
2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
1efdca106c
tilelink: RAMModel support early reuse of source
2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
138276fd87
tilelink: SourceShrinker should work also for 0 latency
2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
b2edca2a6b
tilelink: cut WidthWidget from dependency on addr_lo
2017-07-26 10:31:09 -07:00
Wesley W. Terpstra
ede87c1f73
tilelink: rewrite WidthWidget beat splitter
...
- split the data based on the address, not the mask
(the first version of TileLink did not have low address bits)
- the dependency on addr_lo is now exposed and easy to replace
2017-07-26 10:24:16 -07:00
Wesley W. Terpstra
0f5065fbf3
tilelink: WidthWidget rewrite beat merging
...
- errors are properly OR reduced
- registers latched only as needed (was previously a shift register)
- combines beats without inspecting address (removes addr_lo dependency)
2017-07-26 10:24:12 -07:00
Wesley W. Terpstra
f0ffb7e31e
tilelink: initialize toggle in Fragmenter ( #894 )
...
No strictly necessary, because the initial value does not matter, but good hygiene since it drives a cycle of logic.
2017-07-26 10:21:31 -07:00
Andrew Waterman
5a5b78b15e
Improve L2 TLB coding style
2017-07-26 02:22:43 -07:00
Andrew Waterman
5a9c673f41
Fix L2 TLB response bug
...
Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
2017-07-26 02:20:41 -07:00
Andrew Waterman
acca0fccf5
Fix BTB not being refilled on some indirect jumps
...
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB. That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to. This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow. Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.
This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
2017-07-26 02:13:43 -07:00
Yunsup Lee
6916e5cbfb
coreplex: better names for RocketTiles in Verilog ( #890 )
2017-07-25 16:35:31 -07:00
Andrew Waterman
d43f02268b
Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend
...
Acquire before release; jump in frontend
2017-07-25 16:26:47 -07:00
Wesley W. Terpstra
c2b8b08461
tilelink: fix Fragmenter source re-use bug ( #888 )
...
Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.
However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.
To solve this, we alternate an a.source bit every time D completes a txn.
2017-07-25 16:23:55 -07:00
Andrew Waterman
15878d4691
Perform some control-flow transfers within the Frontend
2017-07-25 15:19:16 -07:00
Andrew Waterman
62c4080585
Add RVC instruction patterns
2017-07-25 15:19:16 -07:00
Andrew Waterman
66d06460fa
Add option for acquire-before-release
2017-07-25 15:19:16 -07:00
Andrew Waterman
86ccd935fc
Add method to print perf events
2017-07-25 15:19:16 -07:00
Andrew Waterman
5df8f0d1ea
Add L2 TLB miss counter
2017-07-25 15:19:16 -07:00
Andrew Waterman
3ced04b70a
Mix in trait to connect global_reset_vector
2017-07-25 15:19:16 -07:00
Yunsup Lee
c9e467a668
coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency ( #887 )
2017-07-25 00:55:55 -07:00
Wesley W. Terpstra
68ed055f6d
chiplink: adjust bus view to include the splitter ( #886 )
2017-07-24 21:41:17 -07:00
Yunsup Lee
dc435af30a
fix HasRTCModuleImp ( #885 )
2017-07-24 20:24:59 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
...
* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Megan Wachs
f2002839eb
TLFragmenter: Continuing my spot battles on requires without explanatory strings ( #882 )
2017-07-21 21:55:32 -07:00
Yunsup Lee
21954c1c73
tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 19:38:27 -07:00
Howard Mao
4d784ad693
add cloneType to RegisterWriteIO and RegisterReadIO ( #874 )
2017-07-18 18:52:31 -07:00
Wesley W. Terpstra
a9c58e9d9f
diplomacy: support creating ShiftQueues as well
2017-07-18 14:57:02 -07:00
Wesley W. Terpstra
c0a3bb58e9
ShiftQueue: use Vec of Bool to support constant prop of enq.valid
2017-07-18 14:56:59 -07:00
Wesley W. Terpstra
416629b3bf
tilelink: FIFOFixer should fix no domain => domain cases ( #873 )
2017-07-17 22:32:17 -07:00
Wesley W. Terpstra
d09a985729
zero: fix attachment in multichannel case ( #870 )
2017-07-17 21:48:31 -07:00
Wesley W. Terpstra
fc75ada577
tilelink: Monitor should report line numbers of connection that failed ( #872 )
2017-07-17 21:29:14 -07:00
Howard Mao
ec57994784
fix the TLFuzzer IO ( #869 )
2017-07-17 14:59:35 -07:00
Wesley W. Terpstra
16e8709144
tilelink: it is now legal to have errors on {Release,Hint}Ack ( #864 )
2017-07-14 16:13:30 -07:00
Richard Xia
9ade7af013
Merge pull request #862 from freechipsproject/plic-max-pri-dts
...
PLIC: Add maxPri as well as ndev in DTS
2017-07-13 17:08:21 -07:00
Richard Xia
f0481801df
Merge pull request #863 from freechipsproject/rename-offchip-interrupts-to-external-interrupts
...
Rename offchip-interrupts to external-interrupts.
2017-07-13 16:52:57 -07:00
Megan Wachs
35464782b5
PLIC: maxPriorities comes from params
2017-07-13 15:57:10 -07:00
Richard Xia
d62787357b
Rename offchip-interrupts to external-interrupts.
2017-07-13 15:56:22 -07:00
Shreesha Srinath
f2533ce825
bootrom: Adding bootrom parameters ( #857 )
...
BootROM parameters currently control the boot rom address, size, and the
hang which essentially sets the reset vector. This commit allows specifying
different parameter values as required.
2017-07-13 13:40:02 -07:00
Megan Wachs
f646bed3ea
PLIC: Use longer DTS name for Max Priorities.
...
I used the singular because there is really only one max priority
2017-07-13 13:37:22 -07:00
Megan Wachs
0800fd3ed9
PLIC: Add maxPri as well as ndev in DTS
2017-07-13 13:18:50 -07:00
Wesley W. Terpstra
b7f1ba3428
tilelink: FIFOFixer must support null cases ( #860 )
...
In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
2017-07-12 22:20:31 -07:00
Wesley W. Terpstra
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
Wesley W. Terpstra
09b9d33a9a
tilelink: FIFOFixer now has a policy parameter
2017-07-12 17:38:55 -07:00
Wesley W. Terpstra
b363a94480
diplomacy: add a new UNCACHEABLE RegionType
2017-07-12 16:31:50 -07:00
Wesley W. Terpstra
c8a7648169
diplomacy: only evaluate a Nexus node's map function once
2017-07-12 16:20:55 -07:00
Wesley W. Terpstra
af3976aa67
regmapper: add byte-sized RegField helper function ( #854 )
2017-07-10 21:08:02 -07:00
Megan Wachs
177ccbb663
regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was ( #855 )
2017-07-10 21:07:50 -07:00
Jim Lawson
287219da06
Merge pull request #851 from freechipsproject/chisel3clock
...
Use chisel3 Clock() method.
2017-07-10 08:33:46 -07:00
Wesley W. Terpstra
5db0e770d5
tilelink: TestSRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
702143eb33
tilelink: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
9310a33e77
apb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
28fbf1af8e
ahb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:39 -07:00
Wesley W. Terpstra
df44b23956
axi4: SRAM can emulate incompletely populated memory
2017-07-07 21:40:39 -07:00
Wesley W. Terpstra
b2cc4b99ed
tilelink: TestSRAM reports errors on illegal access
2017-07-07 21:40:36 -07:00
Wesley W. Terpstra
e8cb6dafd3
tilelink: SRAM reports errors on illegal access
2017-07-07 21:15:36 -07:00
Wesley W. Terpstra
f1fb3be603
ahb: SRAM reports errors on illegal access
2017-07-07 21:15:36 -07:00
Wesley W. Terpstra
19851a7c9e
apb: SRAM reports errors on illegal access
2017-07-07 21:15:33 -07:00
Wesley W. Terpstra
025f7d890b
axi4: SRAM now reports errors on illegal address ( #852 )
2017-07-07 19:27:32 -07:00
Jim Lawson
2bf91a0558
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
...
* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Megan Wachs
76a1ae667f
PLIC: (undefZero=true) Don't allow addresses to alias
...
While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
2017-07-06 17:57:08 -07:00
Andrew Waterman
a0cbc376b4
Merge pull request #849 from freechipsproject/l2-tlb
...
L1 memory system improvements
2017-07-06 13:03:06 -07:00
Andrew Waterman
e1cc0a0a0e
Mask debug interrupts similarly to other interrupts ( #847 )
...
This makes single-step exceptions higher-priority than debug interrupts.
2017-07-06 12:03:24 -07:00
Andrew Waterman
b2351c5fbf
Use consistent casing
2017-07-06 11:16:56 -07:00
Andrew Waterman
be4eceec0d
Fix stupid D$ probe bug
2017-07-06 01:20:47 -07:00
Andrew Waterman
90a7d6a343
Add L2 TLB option
2017-07-06 01:19:18 -07:00
Andrew Waterman
438abc76d2
Handle TL errors in L1 I$
...
Cache the error bit in the tag array; report precisely on access.
2017-07-06 01:02:11 -07:00
Andrew Waterman
0ef45fac9b
Add tag ECC to D$
2017-07-03 18:16:37 -07:00
Andrew Waterman
e9752f76ae
Improve probe state machine
...
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
2017-07-03 16:25:04 -07:00
Richard Xia
5b46350bc3
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 17:44:16 -07:00
Megan Wachs
69ab3626ca
Merge pull request #837 from freechipsproject/plic_recode
...
plic: Recode to use OH knowledge
2017-06-30 16:05:32 -07:00
Megan Wachs
8c92c50d85
plic: make assertion comment right
2017-06-30 14:25:09 -07:00
Megan Wachs
f31ae008f3
plic: Clean up comments and simplify checking
2017-06-30 14:15:26 -07:00
Megan Wachs
76f8de75e3
plic: comment tidying
2017-06-30 12:51:09 -07:00
Megan Wachs
3da26b0aa8
plic: Add some assertions to check one-hot assumptions
2017-06-30 12:32:58 -07:00
Wesley W. Terpstra
367d4aebe6
Set complete unconditionally
2017-06-30 10:15:53 -07:00
Wesley W. Terpstra
4e9f65b2ef
Simplify logic further and bugfix
...
complete was being set unconditionally
2017-06-30 10:07:39 -07:00
Megan Wachs
e8e709c941
plic: Use same recoding technique on complete as well as claim
2017-06-30 08:36:00 -07:00
Wesley W. Terpstra
3dca2bc4a3
gah
2017-06-30 01:07:29 -07:00
Wesley W. Terpstra
e43b7accf9
Fix compile error and eliminate wasteful wires
2017-06-30 01:06:02 -07:00
Megan Wachs
834bcf6b7e
PLIC: simplify some scala code
2017-06-29 19:35:15 -07:00
Megan Wachs
eae4fe1469
plic: Recode to use the knowledge that only one interrupt can be claimed at a time.
2017-06-29 19:09:57 -07:00
Wesley W. Terpstra
e3c7bb3b1f
SRAM: MemoryDevices use .reg (not .reg("mem")) ( #835 )
2017-06-29 19:07:12 -07:00
Megan Wachs
0668f13d99
debug: Fix race between resumereq and resumeack
...
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
2017-06-29 12:27:23 -07:00
Wesley W. Terpstra
5edc4546e3
rocket: add dtim and itim refs to cpus
2017-06-28 23:10:58 -07:00
Wesley W. Terpstra
7d6f8d48f2
Revert "rocket: link dtim to its cpu"
...
This reverts commit e6c2d446cc
.
2017-06-28 23:10:57 -07:00
Wesley W. Terpstra
fbcd6f0eb2
Revert "rocket: link itim to its cpu"
...
This reverts commit 48390ed604
.
2017-06-28 23:10:57 -07:00
Henry Cook
6e5a4c687f
diplomacy: a type of connect that always disables monitors ( #828 )
2017-06-28 21:48:10 -07:00
Megan Wachs
992b480c74
Merge pull request #825 from freechipsproject/debug_wfi
...
Debug + WFI Interactions
2017-06-28 21:28:51 -07:00
Wesley W. Terpstra
66489ffa13
rom+sram: add a compatible field
2017-06-28 15:41:20 -07:00
Wesley W. Terpstra
ca3030cba3
dcache: fix a gender inversion bug introduced in #826
2017-06-28 15:38:53 -07:00
Wesley W. Terpstra
02aa80a958
TLZero: include a version number
2017-06-28 15:12:46 -07:00
Wesley W. Terpstra
48390ed604
rocket: link itim to its cpu
2017-06-28 15:06:19 -07:00