riscv/rocket-chip
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Merge pull request #928 from freechipsproject/critical-paths

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Critical paths
This commit is contained in:
Andrew Waterman 2017-08-06 18:50:59 -07:00 committed by GitHub
commit 7fd8bb1159
2 changed files with 6 additions and 3 deletions
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5
src/main/scala/rocket/DCache.scala
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@ -232,7 +232,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd)
val s2_data_decoded = decodeData(s2_data)
val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
val s2_data_error = needsRead(s2_req) && (s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq)(s2_word_idx)
val s2_data_error = {
val word_errors = s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq
needsRead(s2_req) && (if (usingDataScratchpad) word_errors(s2_word_idx) else word_errors.reduce(_||_))
}
val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt
val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt
val s2_valid_hit_pre_data_ecc = s2_valid_masked && s2_readwrite && !s2_meta_error && s2_hit

4
src/main/scala/rocket/Frontend.scala
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@ -119,8 +119,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val s2_redirect = Wire(init = io.cpu.req.valid)
s2_valid := false
when (!s2_replay && !s2_redirect) {
s2_valid := true
when (!s2_replay) {
s2_valid := !s2_redirect
s2_pc := s1_pc
s2_speculative := s1_speculative
s2_tlb_resp := tlb.io.resp