tilelink: remove obsolete addr_lo signal (#895)
When we first implemented TL, we thought this was helpful, because it made WidthWidgets stateless in all cases. However, it put too much burden on all other masters and slaves, none of which benefitted from this signal. Furthermore, even with addr_lo, WidthWidgets were information lossy because when they widen, they have no information about what to fill in the new high bits of addr_lo.
This commit is contained in:
Wesley W. Terpstra
GitHub
parent
3cceb866cf
commit
9804bdc34e
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@ -53,7 +53,6 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
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d.bits.size := a.bits.size
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d.bits.source := a.bits.source
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d.bits.sink := UInt(0)
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d.bits.addr_lo := a.bits.address
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d.bits.data := UInt(0)
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d.bits.error := a.bits.opcode =/= Hint // Hints may not error
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@ -42,7 +42,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
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val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
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val high = if (wrapSize == size) UInt(0) else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
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in.d.bits := edge.AccessAck(in.a.bits, UInt(0), Mux(high.orR, UInt(0), rom(index)))
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in.d.bits := edge.AccessAck(in.a.bits, Mux(high.orR, UInt(0), rom(index)))
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// Tie off unused channels
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in.b.valid := Bool(false)
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@ -52,7 +52,7 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
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val legal = address.contains(in.a.bits.address)
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val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
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in.d.bits := edge.AccessAck(in.a.bits, UInt(0), !legal)
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in.d.bits := edge.AccessAck(in.a.bits, !legal)
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in.d.bits.data := Cat(mem(memAddress).reverse)
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in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
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when (in.a.fire() && hasData && legal) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) }
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@ -36,7 +36,7 @@ class TLZero(address: AddressSet, resources: Seq[Resource], executable: Boolean
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a.ready := in.d.ready
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in.d.valid := a.valid
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in.d.bits := edge.AccessAck(a.bits, UInt(0))
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in.d.bits := edge.AccessAck(a.bits)
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in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
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// Tie off unused channels
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@ -285,8 +285,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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tl.d.valid := respValid
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tl.d.bits := Mux(edge_in.get.hasData(s1_a),
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edge_in.get.AccessAck(s1_a, UInt(0)),
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edge_in.get.AccessAck(s1_a, UInt(0), UInt(0)))
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edge_in.get.AccessAck(s1_a),
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edge_in.get.AccessAck(s1_a, UInt(0)))
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tl.d.bits.data := s1s3_slaveData
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// Tie off unused channels
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@ -85,8 +85,8 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
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tl_in.d.valid := io.dmem.resp.valid || state === s_grant
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tl_in.d.bits := Mux(acq.opcode.isOneOf(TLMessages.PutFullData, TLMessages.PutPartialData),
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edge.AccessAck(acq, UInt(0)),
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edge.AccessAck(acq, UInt(0), UInt(0)))
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edge.AccessAck(acq),
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edge.AccessAck(acq, UInt(0)))
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tl_in.d.bits.data := Mux(io.dmem.resp.valid, io.dmem.resp.bits.data_raw, acq.data)
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// Tie off unused channels
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@ -133,7 +133,7 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
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in.c.ready := c_probeack || Mux(c_release, releaseack.ready, putfull.ready)
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releaseack.valid := in.c.valid && c_release
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releaseack.bits := edgeIn.ReleaseAck(in.c.bits.address, UInt(0), in.c.bits.source, in.c.bits.size)
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releaseack.bits := edgeIn.ReleaseAck(in.c.bits)
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val put_what = Mux(c_releasedata, TRANSFORM_B, DROP)
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val put_who = Mux(c_releasedata, in.c.bits.source, c_trackerSrc)
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@ -171,7 +171,6 @@ final class TLBundleD(params: TLBundleParameters)
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val size = UInt(width = params.sizeBits)
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val source = UInt(width = params.sourceBits) // to
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val sink = UInt(width = params.sinkBits) // from
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val addr_lo = UInt(width = params.addrLoBits) // instead of mask
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// variable fields during multibeat:
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val data = UInt(width = params.dataBits)
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val error = Bool() // AccessAck[Data], Grant[Data]
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@ -79,7 +79,6 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
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c_d.bits.size := in.c.bits.size
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c_d.bits.source := in.c.bits.source
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c_d.bits.sink := UInt(0)
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c_d.bits.addr_lo := in.c.bits.address
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c_d.bits.data := UInt(0)
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c_d.bits.error := Bool(false)
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@ -61,7 +61,6 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
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dnoise.size := LFSRNoiseMaker(dnoise.params.sizeBits)
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dnoise.source := LFSRNoiseMaker(dnoise.params.sourceBits)
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dnoise.sink := LFSRNoiseMaker(dnoise.params.sinkBits)
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dnoise.addr_lo := LFSRNoiseMaker(dnoise.params.addrLoBits)
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dnoise.data := LFSRNoiseMaker(dnoise.params.dataBits)
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dnoise.error := LFSRNoiseMaker(1)(0)
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@ -144,30 +144,27 @@ class TLEdge(
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}
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}
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def mask(x: TLDataChannel): UInt = {
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def mask(x: TLAddrChannel): UInt = {
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x match {
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case a: TLBundleA => a.mask
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case b: TLBundleB => b.mask
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case c: TLBundleC => mask(c.address, c.size)
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case d: TLBundleD => mask(d.addr_lo, d.size)
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}
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}
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def full_mask(x: TLDataChannel): UInt = {
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def full_mask(x: TLAddrChannel): UInt = {
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x match {
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case a: TLBundleA => mask(a.address, a.size)
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case b: TLBundleB => mask(b.address, b.size)
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case c: TLBundleC => mask(c.address, c.size)
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case d: TLBundleD => mask(d.addr_lo, d.size)
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}
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}
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def address(x: TLDataChannel): UInt = {
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def address(x: TLAddrChannel): UInt = {
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x match {
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case a: TLBundleA => a.address
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case b: TLBundleB => b.address
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case c: TLBundleC => c.address
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case d: TLBundleD => d.addr_lo
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}
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}
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@ -185,7 +182,7 @@ class TLEdge(
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if (manager.beatBytes == 1) UInt(0) else x(log2Ceil(manager.beatBytes)-1, 0)
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def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
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def addr_lo(x: TLDataChannel): UInt = addr_lo(address(x))
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def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
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def numBeats(x: TLChannel): UInt = {
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x match {
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@ -497,42 +494,40 @@ class TLEdgeIn(
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(legal, b)
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}
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def Grant(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromAddress, fromSink, toSource, lgSize, capPermissions, Bool(false))
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def Grant(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, error: Bool) = {
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def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, Bool(false))
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def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, error: Bool) = {
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val d = Wire(new TLBundleD(bundle))
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d.opcode := TLMessages.Grant
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d.param := capPermissions
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d.size := lgSize
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d.source := toSource
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d.sink := fromSink
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d.addr_lo := addr_lo(fromAddress)
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d.data := UInt(0)
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d.error := error
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d
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}
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def Grant(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromAddress, fromSink, toSource, lgSize, capPermissions, data, Bool(false))
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def Grant(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, error: Bool) = {
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def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, Bool(false))
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def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, error: Bool) = {
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val d = Wire(new TLBundleD(bundle))
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d.opcode := TLMessages.GrantData
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d.param := capPermissions
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d.size := lgSize
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d.source := toSource
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d.sink := fromSink
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d.addr_lo := addr_lo(fromAddress)
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d.data := data
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d.error := error
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d
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}
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def ReleaseAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt) = {
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def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size)
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def ReleaseAck(toSource: UInt, lgSize: UInt): TLBundleD = {
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val d = Wire(new TLBundleD(bundle))
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d.opcode := TLMessages.ReleaseAck
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d.param := UInt(0)
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d.size := lgSize
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d.source := toSource
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d.sink := fromSink
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d.addr_lo := addr_lo(fromAddress)
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d.sink := UInt(0)
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d.data := UInt(0)
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d.error := Bool(false)
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d
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@ -623,47 +618,44 @@ class TLEdgeIn(
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(legal, b)
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}
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def AccessAck(a: TLBundleA, fromSink: UInt): TLBundleD = AccessAck(address(a), fromSink, a.source, a.size)
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def AccessAck(a: TLBundleA, fromSink: UInt, error: Bool): TLBundleD = AccessAck(address(a), fromSink, a.source, a.size, error)
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def AccessAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(fromAddress, fromSink, toSource, lgSize, Bool(false))
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def AccessAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt, error: Bool) = {
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def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
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def AccessAck(a: TLBundleA, error: Bool): TLBundleD = AccessAck(a.source, a.size, error)
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def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, Bool(false))
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def AccessAck(toSource: UInt, lgSize: UInt, error: Bool) = {
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val d = Wire(new TLBundleD(bundle))
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d.opcode := TLMessages.AccessAck
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d.param := UInt(0)
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d.size := lgSize
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d.source := toSource
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d.sink := fromSink
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d.addr_lo := addr_lo(fromAddress)
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d.sink := UInt(0)
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d.data := UInt(0)
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d.error := error
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d
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}
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def AccessAck(a: TLBundleA, fromSink: UInt, data: UInt): TLBundleD = AccessAck(address(a), fromSink, a.source, a.size, data)
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def AccessAck(a: TLBundleA, fromSink: UInt, data: UInt, error: Bool): TLBundleD = AccessAck(address(a), fromSink, a.source, a.size, data, error)
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def AccessAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(fromAddress, fromSink, toSource, lgSize, data, Bool(false))
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def AccessAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt, data: UInt, error: Bool) = {
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def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
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def AccessAck(a: TLBundleA, data: UInt, error: Bool): TLBundleD = AccessAck(a.source, a.size, data, error)
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def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, Bool(false))
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def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, error: Bool) = {
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val d = Wire(new TLBundleD(bundle))
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d.opcode := TLMessages.AccessAckData
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d.param := UInt(0)
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d.size := lgSize
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d.source := toSource
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d.sink := fromSink
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d.addr_lo := addr_lo(fromAddress)
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d.sink := UInt(0)
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d.data := data
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d.error := error
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d
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}
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def HintAck(a: TLBundleA, fromSink: UInt): TLBundleD = HintAck(address(a), fromSink, a.source, a.size)
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def HintAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt) = {
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def HintAck(a: TLBundleA): TLBundleD = HintAck(a.source, a.size)
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def HintAck(toSource: UInt, lgSize: UInt) = {
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val d = Wire(new TLBundleD(bundle))
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d.opcode := TLMessages.HintAck
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d.param := UInt(0)
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d.size := lgSize
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d.source := toSource
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d.sink := fromSink
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d.addr_lo := addr_lo(fromAddress)
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d.sink := UInt(0)
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d.data := UInt(0)
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d.error := Bool(false)
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d
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@ -190,7 +190,6 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
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out.d.ready := in.d.ready || drop
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in.d.valid := out.d.valid && !drop
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in.d.bits := out.d.bits // pass most stuff unchanged
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in.d.bits.addr_lo := out.d.bits.addr_lo & ~dsizeOH1
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in.d.bits.source := out.d.bits.source >> addedBits
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in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
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@ -40,7 +40,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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out.a.valid := in.a.valid && !hintBitsAtA
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in.a.ready := Mux(hintBitsAtA, hint.ready, out.a.ready)
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hint.bits := edgeIn.HintAck(in.a.bits, UInt(0))
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hint.bits := edgeIn.HintAck(in.a.bits)
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out.a.bits := in.a.bits
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TLArbiter(TLArbiter.lowestIndexFirst)(in.d, (edgeOut.numBeats1(out.d.bits), out.d), (UInt(0), Queue(hint, 1)))
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@ -232,12 +232,10 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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assert (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
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val source_ok = edge.client.contains(bundle.source)
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val is_aligned = edge.isAligned(bundle.addr_lo, bundle.size)
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val sink_ok = Bool(edge.manager.endSinkId == 0) || bundle.sink < UInt(edge.manager.endSinkId)
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when (bundle.opcode === TLMessages.ReleaseAck) {
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assert (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
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assert (is_aligned, "'D' channel ReleaseAck address not aligned to size" + extra)
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assert (sink_ok, "'D' channel ReleaseAck carries invalid sink ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'D' channel ReleaseAck smaller than a beat" + extra)
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assert (bundle.param === UInt(0), "'D' channel ReleaseeAck carries invalid param" + extra)
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@ -245,7 +243,6 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.Grant) {
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assert (source_ok, "'D' channel Grant carries invalid source ID" + extra)
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assert (is_aligned, "'D' channel Grant address not aligned to size" + extra)
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assert (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'D' channel Grant smaller than a beat" + extra)
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assert (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
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@ -253,7 +250,6 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.GrantData) {
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assert (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
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assert (is_aligned, "'D' channel GrantData address not aligned to size" + extra)
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assert (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'D' channel GrantData smaller than a beat" + extra)
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assert (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
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@ -261,7 +257,6 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.AccessAck) {
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assert (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
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assert (is_aligned, "'D' channel AccessAck address not aligned to size" + extra)
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assert (sink_ok, "'D' channel AccessAck carries invalid sink ID" + extra)
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// size is ignored
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assert (bundle.param === UInt(0), "'D' channel AccessAck carries invalid param" + extra)
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@ -269,7 +264,6 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.AccessAckData) {
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assert (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
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assert (is_aligned, "'D' channel AccessAckData address not aligned to size" + extra)
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assert (sink_ok, "'D' channel AccessAckData carries invalid sink ID" + extra)
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// size is ignored
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assert (bundle.param === UInt(0), "'D' channel AccessAckData carries invalid param" + extra)
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@ -277,7 +271,6 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
|
|||
|
||||
when (bundle.opcode === TLMessages.HintAck) {
|
||||
assert (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
|
||||
assert (is_aligned, "'D' channel HintAck address not aligned to size" + extra)
|
||||
assert (sink_ok, "'D' channel HintAck carries invalid sink ID" + extra)
|
||||
// size is ignored
|
||||
assert (bundle.param === UInt(0), "'D' channel HintAck carries invalid param" + extra)
|
||||
|
|
@ -379,14 +372,12 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
|
|||
val size = Reg(UInt())
|
||||
val source = Reg(UInt())
|
||||
val sink = Reg(UInt())
|
||||
val addr_lo = Reg(UInt())
|
||||
when (d.valid && !d_first) {
|
||||
assert (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
|
||||
assert (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
|
||||
assert (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
|
||||
assert (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
|
||||
assert (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
|
||||
assert (d.bits.addr_lo=== addr_lo,"'D' channel addr_lo changed with multibeat operation" + extra)
|
||||
}
|
||||
when (d.fire() && d_first) {
|
||||
opcode := d.bits.opcode
|
||||
|
|
@ -394,7 +385,6 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
|
|||
size := d.bits.size
|
||||
source := d.bits.source
|
||||
sink := d.bits.sink
|
||||
addr_lo := d.bits.addr_lo
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -47,15 +47,14 @@ class TLRegisterNode(
|
|||
val baseEnd = 0
|
||||
val (sizeEnd, sizeOff) = (edge.bundle.sizeBits + baseEnd, baseEnd)
|
||||
val (sourceEnd, sourceOff) = (edge.bundle.sourceBits + sizeEnd, sizeEnd)
|
||||
val (addrLoEnd, addrLoOff) = (log2Up(beatBytes) + sourceEnd, sourceEnd)
|
||||
|
||||
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, addrLoEnd)
|
||||
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, sourceEnd)
|
||||
val in = Wire(Decoupled(new RegMapperInput(params)))
|
||||
in.bits.read := a.bits.opcode === TLMessages.Get
|
||||
in.bits.index := edge.addr_hi(a.bits)
|
||||
in.bits.data := a.bits.data
|
||||
in.bits.mask := a.bits.mask
|
||||
in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size)
|
||||
in.bits.extra := Cat(a.bits.source, a.bits.size)
|
||||
|
||||
// Invoke the register map builder
|
||||
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
|
||||
|
|
@ -66,10 +65,8 @@ class TLRegisterNode(
|
|||
d.valid := out.valid
|
||||
out.ready := d.ready
|
||||
|
||||
// We must restore the size and addr_lo to enable width adapters to work
|
||||
// We must restore the size to enable width adapters to work
|
||||
d.bits := edge.AccessAck(
|
||||
fromAddress = out.bits.extra(addrLoEnd-1, addrLoOff),
|
||||
fromSink = UInt(0), // our unique sink id
|
||||
toSource = out.bits.extra(sourceEnd-1, sourceOff),
|
||||
lgSize = out.bits.extra(sizeEnd-1, sizeOff))
|
||||
|
||||
|
|
|
|||
|
|
@ -51,7 +51,6 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4,
|
|||
val d_read = Reg(Bool())
|
||||
val d_size = Reg(UInt())
|
||||
val d_source = Reg(UInt())
|
||||
val d_addr = Reg(UInt())
|
||||
val d_data = Wire(UInt())
|
||||
val d_legal = Reg(Bool())
|
||||
|
||||
|
|
@ -61,7 +60,7 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4,
|
|||
in.d.valid := d_full
|
||||
in.a.ready := in.d.ready || !d_full
|
||||
|
||||
in.d.bits := edge.AccessAck(d_addr, UInt(0), d_source, d_size, !d_legal)
|
||||
in.d.bits := edge.AccessAck(d_source, d_size, !d_legal)
|
||||
// avoid data-bus Mux
|
||||
in.d.bits.data := d_data
|
||||
in.d.bits.opcode := Mux(d_read, TLMessages.AccessAckData, TLMessages.AccessAck)
|
||||
|
|
@ -74,7 +73,6 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4,
|
|||
d_read := read
|
||||
d_size := in.a.bits.size
|
||||
d_source := in.a.bits.source
|
||||
d_addr := edge.addr_lo(in.a.bits)
|
||||
d_legal := a_legal
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -170,7 +170,6 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
|
|||
val d_error = Reg(Bool())
|
||||
val d_write = RegEnable(send.write, out.hreadyout)
|
||||
val d_source = RegEnable(send.source, out.hreadyout)
|
||||
val d_addr = RegEnable(send.addr, out.hreadyout)
|
||||
val d_size = RegEnable(send.size, out.hreadyout)
|
||||
|
||||
when (out.hreadyout) {
|
||||
|
|
@ -180,7 +179,7 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
|
|||
}
|
||||
|
||||
d.valid := d_valid && out.hreadyout
|
||||
d.bits := edgeIn.AccessAck(d_addr, UInt(0), d_source, d_size, out.hrdata, out.hresp || d_error)
|
||||
d.bits := edgeIn.AccessAck(d_source, d_size, out.hrdata, out.hresp || d_error)
|
||||
d.bits.opcode := Mux(d_write, TLMessages.AccessAck, TLMessages.AccessAckData)
|
||||
|
||||
// AHB has no cache coherence
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod
|
|||
d.valid := a_enable && out.pready
|
||||
assert (!d.valid || d.ready)
|
||||
|
||||
d.bits := edgeIn.AccessAck(a.bits, UInt(0), out.prdata, out.pslverr)
|
||||
d.bits := edgeIn.AccessAck(a.bits, out.prdata, out.pslverr)
|
||||
d.bits.opcode := Mux(a_write, TLMessages.AccessAck, TLMessages.AccessAckData)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -93,18 +93,16 @@ class TLToAXI4(beatBytes: Int, combinational: Boolean = true, adapterName: Optio
|
|||
ElaborationArtefacts.add(s"${n}.axi4.json", s"""{"mapping":[${maps.mkString(",")}]}""")
|
||||
}
|
||||
|
||||
// We need to keep the following state from A => D: (addr_lo, size, source)
|
||||
// We need to keep the following state from A => D: (size, source)
|
||||
// All of those fields could potentially require 0 bits (argh. Chisel.)
|
||||
// We will pack all of that extra information into the user bits.
|
||||
|
||||
val sourceBits = log2Ceil(edgeIn.client.endSourceId)
|
||||
val sizeBits = log2Ceil(edgeIn.maxLgSize+1)
|
||||
val addrBits = log2Ceil(edgeIn.manager.beatBytes)
|
||||
val stateBits = addrBits + sizeBits + sourceBits // could be 0
|
||||
val stateBits = sizeBits + sourceBits // could be 0
|
||||
require (stateBits <= out.aw.bits.params.userBits)
|
||||
|
||||
val a_address = edgeIn.address(in.a.bits)
|
||||
val a_addr_lo = edgeIn.addr_lo(a_address)
|
||||
val a_source = in.a.bits.source
|
||||
val a_size = edgeIn.size(in.a.bits)
|
||||
val a_isPut = edgeIn.hasData(in.a.bits)
|
||||
|
|
@ -113,26 +111,22 @@ class TLToAXI4(beatBytes: Int, combinational: Boolean = true, adapterName: Optio
|
|||
// Make sure the fields are within the bounds we assumed
|
||||
assert (a_source < UInt(BigInt(1) << sourceBits))
|
||||
assert (a_size < UInt(BigInt(1) << sizeBits))
|
||||
assert (a_addr_lo < UInt(BigInt(1) << addrBits))
|
||||
|
||||
// Carefully pack/unpack fields into the state we send
|
||||
val baseEnd = 0
|
||||
val (sourceEnd, sourceOff) = (sourceBits + baseEnd, baseEnd)
|
||||
val (sizeEnd, sizeOff) = (sizeBits + sourceEnd, sourceEnd)
|
||||
val (addrEnd, addrOff) = (addrBits + sizeEnd, sizeEnd)
|
||||
require (addrEnd == stateBits)
|
||||
require (sizeEnd == stateBits)
|
||||
|
||||
val a_state = (a_source << sourceOff) | (a_size << sizeOff) | (a_addr_lo << addrOff)
|
||||
val a_state = (a_source << sourceOff) | (a_size << sizeOff)
|
||||
|
||||
val r_state = out.r.bits.user.getOrElse(UInt(0))
|
||||
val r_source = if (sourceBits > 0) r_state(sourceEnd-1, sourceOff) else UInt(0)
|
||||
val r_size = if (sizeBits > 0) r_state(sizeEnd -1, sizeOff) else UInt(0)
|
||||
val r_addr_lo = if (addrBits > 0) r_state(addrEnd -1, addrOff) else UInt(0)
|
||||
|
||||
val b_state = out.b.bits.user.getOrElse(UInt(0))
|
||||
val b_source = if (sourceBits > 0) b_state(sourceEnd-1, sourceOff) else UInt(0)
|
||||
val b_size = if (sizeBits > 0) b_state(sizeEnd -1, sizeOff) else UInt(0)
|
||||
val b_addr_lo = if (addrBits > 0) b_state(addrEnd -1, addrOff) else UInt(0)
|
||||
|
||||
// We need these Queues because AXI4 queues are irrevocable
|
||||
val depth = if (combinational) 1 else 2
|
||||
|
|
@ -188,8 +182,8 @@ class TLToAXI4(beatBytes: Int, combinational: Boolean = true, adapterName: Optio
|
|||
val r_error = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
|
||||
val b_error = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY
|
||||
|
||||
val r_d = edgeIn.AccessAck(r_addr_lo, UInt(0), r_source, r_size, UInt(0), r_error)
|
||||
val b_d = edgeIn.AccessAck(b_addr_lo, UInt(0), b_source, b_size, b_error)
|
||||
val r_d = edgeIn.AccessAck(r_source, r_size, UInt(0), r_error)
|
||||
val b_d = edgeIn.AccessAck(b_source, b_size, b_error)
|
||||
|
||||
in.d.bits := Mux(r_wins, r_d, b_d)
|
||||
in.d.bits.data := out.r.bits.data // avoid a costly Mux
|
||||
|
|
|
|||
Loading…
Reference in New Issue