riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Shave a gate delay off I$ backpressure path

Browse Source 
The deleted code was a holdover from Hwacha's vector fences.
This commit is contained in:
Andrew Waterman 2017-08-04 00:40:18 -07:00
parent ecc2ee366c
commit 06a831310b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/RocketCore.scala
View File

@ -596,7 +596,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
io.imem.sfence.bits.asid := wb_reg_rs2
io.ptw.sfence := io.imem.sfence
ibuf.io.inst(0).ready := !ctrl_stalld || csr.io.interrupt
ibuf.io.inst(0).ready := !ctrl_stalld
io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken))
io.imem.btb_update.bits.isValid := !mem_reg_replay && mem_cfi