riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #906 from freechipsproject/critical-paths

Browse Source 
Mitigate I$->D$->I$ critical path
This commit is contained in:
Yunsup Lee
2017-07-31 16:14:11 -07:00
committed by GitHub
parent 07b4edfc87 d811692c3b
commit 7adfd5c431
1 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/rocket/Frontend.scala
View File

@@ -93,7 +93,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
val s2_btb_resp_bits = Reg(new BTBResp)
val s2_tlb_resp = Reg(tlb.io.resp)
val s2_xcpt = !s2_tlb_resp.miss && fq.io.enq.bits.xcpt.asUInt.orR
val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst
val s2_speculative = Reg(init=Bool(false))
val s2_partial_insn_valid = RegInit(false.B)
val s2_partial_insn = Reg(UInt(width = coreInstBits))
@@ -140,9 +140,9 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s2_vaddr := s2_pc
icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay
icache.io.s2_kill := s2_valid && (s2_speculative && !s2_tlb_resp.cacheable || s2_xcpt)
icache.io.s2_kill := s2_speculative && !s2_tlb_resp.cacheable || s2_xcpt
fq.io.enq.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill)
fq.io.enq.valid := s2_valid && (icache.io.resp.valid || !s2_tlb_resp.miss && icache.io.s2_kill)
fq.io.enq.bits.pc := s2_pc
io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc))