riscv/rocket-chip
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Fix L2 TLB perfctr

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It was counting conflict misses but not cold misses.
This commit is contained in:
Andrew Waterman 2017-08-04 17:01:31 -07:00
parent df7f09b9ce
commit 8d97684555
1 changed files with 7 additions and 5 deletions
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12
src/main/scala/rocket/PTW.scala
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@ -176,17 +176,19 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
val s0_valid = !l2_refill && arb.io.out.fire()
val s1_valid = RegNext(s0_valid)
val s2_valid = RegNext(s1_valid && valid(r_idx))
val s2_valid = RegNext(s1_valid)
val s1_rdata = ram.read(arb.io.out.bits.addr(idxBits-1, 0), s0_valid)
val s2_rdata = code.decode(RegEnable(s1_rdata, s1_valid))
when (s2_valid && s2_rdata.error) { valid := 0.U }
val s2_valid_bit = RegEnable(valid(r_idx), s1_valid)
val s2_g = RegEnable(g(r_idx), s1_valid)
when (s2_valid && s2_valid_bit && s2_rdata.error) { valid := 0.U }
val s2_entry = s2_rdata.uncorrected.asTypeOf(new Entry)
val s2_hit = s2_valid && !s2_rdata.error && r_tag === s2_entry.tag
io.dpath.perf.l2miss := s2_valid && !(r_tag === s2_entry.tag)
val s2_hit = s2_valid && s2_valid_bit && !s2_rdata.error && r_tag === s2_entry.tag
io.dpath.perf.l2miss := s2_valid && !(s2_valid_bit && r_tag === s2_entry.tag)
val s2_pte = Wire(new PTE)
s2_pte := s2_entry
s2_pte.g := g(r_idx)
s2_pte.g := s2_g
s2_pte.v := true
(s2_hit, s2_pte)