Merge pull request #933 from freechipsproject/cinst
Print out the compressed instruction when executing one
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commit
6d1d285464
@ -16,6 +16,7 @@ class Instruction(implicit val p: Parameters) extends ParameterizedBundle with H
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val rvc = Bool()
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val inst = new ExpandedInstruction
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val raw = UInt(width = 32)
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val cinst = UInt(width = 32)
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require(coreInstBits == (if (usingCompressed) 16 else 32))
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}
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@ -95,6 +96,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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exp.io.in := curInst
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io.inst(i).bits.inst := exp.io.out
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io.inst(i).bits.raw := curInst
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io.inst(i).bits.cinst := Mux(exp.io.rvc, curInst & 0xFFFF, curInst)
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if (usingCompressed) {
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val replay = ic_replay(j) || (!exp.io.rvc && (btbHitMask(j) || ic_replay(j+1)))
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@ -136,6 +136,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val ex_reg_replay = Reg(Bool())
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val ex_reg_pc = Reg(UInt())
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val ex_reg_inst = Reg(Bits())
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val ex_reg_cinst = Reg(Bits())
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val mem_reg_xcpt_interrupt = Reg(Bool())
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val mem_reg_valid = Reg(Bool())
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@ -152,6 +153,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val mem_reg_sfence = Reg(Bool())
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val mem_reg_pc = Reg(UInt())
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val mem_reg_inst = Reg(Bits())
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val mem_reg_cinst = Reg(Bits())
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val mem_reg_wdata = Reg(Bits())
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val mem_reg_rs2 = Reg(Bits())
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val take_pc_mem = Wire(Bool())
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@ -165,6 +167,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val wb_reg_sfence = Reg(Bool())
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val wb_reg_pc = Reg(UInt())
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val wb_reg_inst = Reg(Bits())
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val wb_reg_cinst = Reg(Bits())
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val wb_reg_wdata = Reg(Bits())
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val wb_reg_rs2 = Reg(Bits())
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val take_pc_wb = Wire(Bool())
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@ -175,6 +178,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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// decode stage
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val ibuf = Module(new IBuf)
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val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
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val id_nonexpanded_inst = ibuf.io.inst.map(_.bits.cinst)
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val id_inst = id_expanded_inst.map(_.bits)
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ibuf.io.imem <> io.imem.resp
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ibuf.io.kill := take_pc
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@ -340,6 +344,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {
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ex_reg_cause := id_cause
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ex_reg_inst := id_inst(0)
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ex_reg_cinst := id_nonexpanded_inst(0)
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ex_reg_pc := ibuf.io.pc
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ex_reg_btb_resp := ibuf.io.btb_resp
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}
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@ -400,6 +405,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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mem_reg_cause := ex_cause
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mem_reg_inst := ex_reg_inst
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mem_reg_cinst := ex_reg_cinst
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mem_reg_pc := ex_reg_pc
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mem_reg_wdata := alu.io.out
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@ -447,6 +453,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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}
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wb_reg_cause := mem_cause
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wb_reg_inst := mem_reg_inst
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wb_reg_cinst := mem_reg_cinst
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wb_reg_pc := mem_reg_pc
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}
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@ -660,6 +667,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val pc = Wire(SInt(width=xLen))
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pc := wb_reg_pc.asSInt
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val inst = wb_reg_inst
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val cinst = wb_reg_cinst
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val rd = RegNext(RegNext(RegNext(id_waddr)))
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val wfd = wb_ctrl.wfd
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val wxd = wb_ctrl.wxd
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@ -668,16 +676,16 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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when (wb_valid) {
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when (wfd) {
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printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd+UInt(32))
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printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, cinst, rd, rd+UInt(32))
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}
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.elsewhen (wxd && rd =/= UInt(0) && has_data) {
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printf ("%d 0x%x (0x%x) x%d 0x%x\n", priv, pc, inst, rd, rf_wdata)
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printf ("%d 0x%x (0x%x) x%d 0x%x\n", priv, pc, cinst, rd, rf_wdata)
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}
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.elsewhen (wxd && rd =/= UInt(0) && !has_data) {
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printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd)
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printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, cinst, rd, rd)
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}
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.otherwise {
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printf ("%d 0x%x (0x%x)\n", priv, pc, inst)
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printf ("%d 0x%x (0x%x)\n", priv, pc, cinst)
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}
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}
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@ -691,7 +699,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0)), rf_wdata, rf_wen,
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wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
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wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
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wb_reg_inst, wb_reg_inst)
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wb_reg_cinst, wb_reg_cinst)
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}
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def checkExceptions(x: Seq[(Bool, UInt)]) =
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