tilelink: Error device supports Acquire

We need this if we want to divert traffic to it from a TL-C slave.

src/main/scala/amba/axi4/Test.scala

@@ -98,10 +98,10 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
   val node = AXI4InputNode()
   val xbar = LazyModule(new TLXbar)
   val ram  = LazyModule(new TLRAM(fuzzAddr))
-  val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)))))
+  val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256)))
 
   ram.node   := TLFragmenter(4, 16)(xbar.node)
-  error.node := TLFragmenter(4, 16)(xbar.node)
+  error.node := xbar.node
 
   xbar.node :=
     TLFIFOFixer()(

src/main/scala/coreplex/SystemBus.scala

@@ -36,6 +36,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   val toMemoryBus: TLOutwardNode = outwardNode
 
+  val toSlave: TLOutwardNode = outwardNode
+
   def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = {
     val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
     inwardNode :=* sink.node

src/main/scala/devices/tilelink/Error.scala

@@ -4,13 +4,13 @@ package freechips.rocketchip.devices.tilelink
 
 import Chisel._
 import freechips.rocketchip.config.{Field, Parameters}
-import freechips.rocketchip.coreplex.HasPeripheryBus
+import freechips.rocketchip.coreplex.HasSystemBus
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import scala.math.min
 
-case class ErrorParams(address: Seq[AddressSet])
+case class ErrorParams(address: Seq[AddressSet], maxTransfer: Int = 4096)
 case object ErrorParams extends Field[ErrorParams]
 
 /** Adds a /dev/null slave that generates TL error response messages */
@@ -20,18 +20,23 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
 
   val device = new SimpleDevice("error-device", Seq("sifive,error0"))
 
+  val xfer = TransferSizes(1, params.maxTransfer)
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = address,
       resources          = device.reg("mem"),
-      supportsGet        = TransferSizes(1, beatBytes),
-      supportsPutPartial = TransferSizes(1, beatBytes),
-      supportsPutFull    = TransferSizes(1, beatBytes),
-      supportsArithmetic = TransferSizes(1, beatBytes),
-      supportsLogical    = TransferSizes(1, beatBytes),
-      supportsHint       = TransferSizes(1, beatBytes),
+      regionType         = RegionType.UNCACHED,
+      supportsAcquireT   = xfer,
+      supportsAcquireB   = xfer,
+      supportsGet        = xfer,
+      supportsPutPartial = xfer,
+      supportsPutFull    = xfer,
+      supportsArithmetic = xfer,
+      supportsLogical    = xfer,
+      supportsHint       = xfer,
       fifoId             = Some(0))), // requests are handled in order
     beatBytes  = beatBytes,
+    endSinkId  = 1, // can receive GrantAck
     minLatency = 1))) // no bypass needed for this device
 
   lazy val module = new LazyModuleImp(this) {
@@ -40,35 +45,57 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
     }
 
     import TLMessages._
-    val opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck)
+    import TLPermissions._
 
+    val edge = node.edgesIn(0)
     val in = io.in(0)
     val a = Queue(in.a, 1)
-    val d = in.d
+    val c = Queue(in.c, 1)
+    val da = Wire(in.d)
+    val dc = Wire(in.d)
 
-    a.ready := d.ready
-    d.valid := a.valid
-    d.bits.opcode  := opcodes(a.bits.opcode)
-    d.bits.param   := UInt(0)
-    d.bits.size    := a.bits.size
-    d.bits.source  := a.bits.source
-    d.bits.sink    := UInt(0)
-    d.bits.data    := UInt(0)
-    d.bits.error   := a.bits.opcode =/= Hint // Hints may not error
+    val a_last = edge.last(a)
+    val c_last = edge.last(c)
+    val da_last = edge.last(da)
+    val dc_last = edge.last(dc)
 
-    // Tie off unused channels
+    a.ready := (da.ready && da_last) || !a_last
+    da.valid := a.valid && a_last
+
+    val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant)
+    da.bits.opcode  := a_opcodes(a.bits.opcode)
+    da.bits.param   := UInt(0)
+    da.bits.size    := a.bits.size
+    da.bits.source  := a.bits.source
+    da.bits.sink    := UInt(0)
+    da.bits.data    := UInt(0)
+    da.bits.error   := Bool(true)
+
+    c.ready := (dc.ready && dc_last) || !c_last
+    dc.valid := c.valid && c_last
+
+    dc.bits.opcode := ReleaseAck
+    dc.bits.param  := Vec(toN, toN, toB)(c.bits.param)
+    dc.bits.size   := c.bits.size
+    dc.bits.source := c.bits.source
+    dc.bits.sink   := UInt(0)
+    dc.bits.data   := UInt(0)
+    dc.bits.error  := Bool(true)
+
+    // Combine response channels
+    TLArbiter.lowest(edge, in.d, dc, da)
+
+    // We never probe or issue B requests; we are UNCACHED
     in.b.valid := Bool(false)
-    in.c.ready := Bool(true)
+
+    // Sink GrantAcks
     in.e.ready := Bool(true)
   }
 }
 
-trait HasPeripheryErrorSlave extends HasPeripheryBus {
+trait HasSystemErrorSlave extends HasSystemBus {
   private val params = p(ErrorParams)
-  private val maxXfer = min(params.address.map(_.alignment).max.toInt, 4096)
-  val error = LazyModule(new TLError(params, pbus.beatBytes))
+  val error = LazyModule(new TLError(params, sbus.beatBytes))
 
-  // Most slaves do not support a 4kB burst so this slave ends up with many more source bits than others;
-  // we exclude the onerously large TLMonitor that results.
-  error.node connectButDontMonitor pbus.toLargeBurstSlave(maxXfer)
+  error.node := sbus.toSlave
 }

src/main/scala/system/ExampleRocketSystem.scala

@@ -14,7 +14,7 @@ class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
     with HasMasterAXI4MMIOPort
     with HasSlaveAXI4Port
     with HasPeripheryBootROM
-    with HasPeripheryErrorSlave {
+    with HasSystemErrorSlave {
   override lazy val module = new ExampleRocketSystemModule(this)
 }