shift regs: remove some unnecessary primitives, and add some that actually are necessary
This commit is contained in:
Megan Wachs
parent
777f052f95
commit
3c4b472f66
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@ -4,78 +4,34 @@ package freechips.rocketchip.util
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import Chisel._
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object ShiftReg {
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/** Similar to Chisel ShiftRegister, but allows the user to
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* specify a name and initial value. This is different from
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* ShiftRegInit in that it allows the enable signal to be specified.
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* Returns the n-cycle delayed version of the input signal.
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*
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* @param in input to delay
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* @param n number of cycles to delay
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* @param en enable the shift
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* @param name set the elaborated name of the registers.
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*/
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def apply[T <: Chisel.Data](in: T,
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n: Int,
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en: Chisel.Bool = Chisel.Bool(true),
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name: Option[String] = None): T = {
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// The order of tests reflects the expected use cases.
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if (n != 0) {
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val r = Chisel.RegEnable(apply(in, n-1, en, name), en)
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name.foreach { na => r.suggestName(s"${na}_pipe_${n-1}") }
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r
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} else {
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in
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}
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}
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/** Returns the n-cycle delayed version of the input signal with reset initialization.
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*
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* @param in input to delay
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* @param n number of cycles to delay
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* @param init reset value for each register in the shift
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* @param en enable the shift
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* @param name set the elaborated name of the registers.
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*/
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def apply[T <: Chisel.Data](in: T, n: Int, init: T, en: Chisel.Bool, name: Option[String]): T = {
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// The order of tests reflects the expected use cases.
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if (n != 0) {
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val r = Chisel.RegEnable(apply(in, n-1, init, en, name), init, en)
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if (name.isDefined) r.suggestName(s"${name.get}_pipe_${n-1}")
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r
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} else {
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in
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}
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}
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def apply[T <: Chisel.Data](in: T, n: Int, init: T, name: Option[String]): T = {
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apply(in, n, en = Bool(true), name)
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}
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}
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// Similar to the Chisel ShiftRegister but allows the user to suggest a
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// name to the registers that get instantiated, and
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// to provide a reset value.
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object ShiftRegInit {
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def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
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ShiftReg(in, n, init, en = Bool(true), name)
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(0 until n).foldLeft(in) {
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case (next, i) => {
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val r = Reg(next, next = next, init = init)
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name.foreach { na => r.suggestName(s"${na}_${i}") }
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r
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}
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}
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}
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/** These wrap behavioral
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* shift registers into specific
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* modules to allow for
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* shift registers into specific modules to allow for
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* backend flows to replace or constrain
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* them properly when used for CDC synchronization,
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* rather than buffering.
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*
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* The 3 different types vary in their reset behavior:
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* The different types vary in their reset behavior:
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* AsyncResetShiftReg -- This is identical to the AsyncResetSynchronizerShiftReg,
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* it is just named differently
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* to distinguish its use case. This is a ShiftRegister meant for timing,
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* it is just named differently to distinguish its use case.
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* This is an async ShiftRegister meant for timing,
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* not for synchronization.
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* AsyncResetSynchronizerShiftReg -- asynchronously reset to 0
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* SynchronizerShiftReg -- no reset, pipeline only.
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*
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* AsyncResetSynchronizerShiftReg -- asynchronously reset to specific value.
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* SyncResetSynchronizerShiftReg -- reset to specific value.
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* SynchronizerShiftReg -- no reset, pipeline only.
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*/
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abstract class AbstractPipelineReg(w: Int = 1) extends Module {
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@ -114,20 +70,38 @@ class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String
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}
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object AsyncResetShiftReg {
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def apply [T <: Chisel.Data](in: T, depth: Int = 1, init: Int = 0, name: Option[String] = None ): T =
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def apply [T <: Chisel.Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
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AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, name: Option[String]): T =
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apply(in, depth, 0, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: T, name: Option[String]): T =
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apply(in, depth, init.litValue.toInt, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: T): T =
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apply (in, depth, init.litValue.toInt, None)
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}
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// Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does
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// not try to merge instances of this with instances of the superclass.
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class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AsyncResetShiftReg(w, depth = sync, name = "sync") {
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class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3, init: Int = 0) extends AsyncResetShiftReg(w, depth = sync, init, name = "sync") {
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require(sync > 0, "Sync must be greater than 0.")
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override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
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override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
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}
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object AsyncResetSynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
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AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync), in, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
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AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, depth, init), in, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, name: Option[String]): T =
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apply(in, depth, 0, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: T, name: Option[String]): T =
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apply(in, depth, init.litValue.toInt, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: T): T =
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apply (in, depth, init.litValue.toInt, None)
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}
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class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
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@ -148,7 +122,22 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineRe
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io.q := syncv.head
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}
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object SynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
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AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
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}
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class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3, init: Int = 0) extends AbstractPipelineReg(w) {
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require (sync >= 0, "Sync must be greater than or equal to 0")
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override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
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io.q := ShiftRegInit(io.d, n = sync, init = init.U, name = Some("sync"))
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}
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object SyncResetSynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, init: T, name: Option[String] = None): T =
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AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init.litValue.toInt), in, name)
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}
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