diplomacy: provide default clock/reset for LazyRawModuleImp
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@ -3,7 +3,7 @@
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package freechips.rocketchip.diplomacy
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import Chisel._
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import chisel3.experimental.{BaseModule, RawModule, MultiIOModule}
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import chisel3.experimental.{BaseModule, RawModule, MultiIOModule, withClockAndReset}
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import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
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import freechips.rocketchip.config.Parameters
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@ -151,13 +151,19 @@ trait LazyModuleImpLike extends BaseModule
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override def desiredName = wrapper.moduleName
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suggestName(wrapper.instanceName)
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wrapper.instantiate()
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implicit val p = wrapper.p
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}
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abstract class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike
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abstract class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
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wrapper.instantiate()
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}
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abstract class LazyMultiIOModuleImp(val wrapper: LazyModule) extends MultiIOModule with LazyModuleImpLike
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abstract class LazyMultiIOModuleImp(val wrapper: LazyModule) extends MultiIOModule with LazyModuleImpLike {
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wrapper.instantiate()
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}
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abstract class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike
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abstract class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
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withClockAndReset(Bool(false).asClock, Bool(true)) {
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wrapper.instantiate()
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}
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}
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