riscv/rocket-chip
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Don't block D-channel when handling a probe

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This is an acquire-before-release regression.
This commit is contained in:
Andrew Waterman 2017-08-12 16:13:24 -07:00
parent 604abd5b07
commit 7387f2a93a
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/DCache.scala
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@ -411,7 +411,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val grantInProgress = Reg(init=Bool(false))
val blockProbeAfterGrantCount = Reg(init=UInt(0))
when (blockProbeAfterGrantCount > 0) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1 }
val canAcceptCachedGrant = if (cacheParams.acquireBeforeRelease) release_state === s_ready else true.B
val canAcceptCachedGrant = if (cacheParams.acquireBeforeRelease) !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta) else true.B
tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B)
when (tl_out.d.fire()) {
when (grantIsCached) {