riscv/rocket-chip
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Don't refill BTB on not-taken branches

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This commit is contained in:
Andrew Waterman 2017-07-28 13:13:52 -07:00
parent 2e8b02e780
commit 4c82f6b77e
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/RocketCore.scala
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@ -593,7 +593,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
ibuf.io.inst(0).ready := !ctrl_stalld || csr.io.interrupt
io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && mem_misprediction)
io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken))
io.imem.btb_update.bits.isValid := !mem_reg_replay && mem_cfi
io.imem.btb_update.bits.cfiType :=
Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call,