riscv/rocket-chip
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Revert "tile: add option for tile boundary buffers"

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This reverts commit b64b87ad07.

The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
This commit is contained in:
Wesley W. Terpstra
2017-07-29 00:03:24 -07:00
parent 68064ba260
commit eadf4e9fcc
1 changed files with 7 additions and 12 deletions
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19
src/main/scala/tile/RocketTile.scala
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@@ -17,8 +17,7 @@ case class RocketTileParams(
dcache: Option[DCacheParams] = Some(DCacheParams()),
rocc: Seq[RoCCParams] = Nil,
btb: Option[BTBParams] = Some(BTBParams()),
dataScratchpadBytes: Int = 0,
boundaryBufferParams: BufferParams = BufferParams.flow) extends TileParams {
dataScratchpadBytes: Int = 0) extends TileParams {
require(icache.isDefined)
require(dcache.isDefined)
}
@@ -172,11 +171,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
val periphIntNode = IntInputNode()
val coreIntNode = IntInputNode()
val intXbar = LazyModule(new IntXbar)
val masterBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
val slaveBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
masterBuffer.node :=* rocket.masterNode
rocket.slaveNode connectButDontMonitorSlaves slaveBuffer.node
rocket.intNode := intXbar.intnode
lazy val module = new LazyModuleImp(this) {
@@ -195,10 +190,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLOutputNode()
masterNode :=* masterBuffer.node
masterNode :=* rocket.masterNode
val slaveNode = new TLInputNode() { override def reverse = true }
slaveBuffer.node connectButDontMonitorSlaves slaveNode
rocket.slaveNode connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers.
// Others need no synchronization.
@@ -213,12 +208,12 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLAsyncOutputNode()
val source = LazyModule(new TLAsyncCrossingSource)
source.node :=* masterBuffer.node
source.node :=* rocket.masterNode
masterNode :=* source.node
val slaveNode = new TLAsyncInputNode() { override def reverse = true }
val sink = LazyModule(new TLAsyncCrossingSink)
slaveBuffer.node connectButDontMonitorSlaves sink.node
rocket.slaveNode connectButDontMonitorSlaves sink.node
sink.node connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers,
@@ -237,12 +232,12 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLRationalOutputNode()
val source = LazyModule(new TLRationalCrossingSource)
source.node :=* masterBuffer.node
source.node :=* rocket.masterNode
masterNode :=* source.node
val slaveNode = new TLRationalInputNode() { override def reverse = true }
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
slaveBuffer.node connectButDontMonitorSlaves sink.node
rocket.slaveNode connectButDontMonitorSlaves sink.node
sink.node connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers.