riscv/rocket-chip
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Get L2 TLB tag/parity check off the D$ arbitration path

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This commit is contained in:
Andrew Waterman 2017-08-04 17:01:51 -07:00
parent 8d97684555
commit 6112adfbb0
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/rocket/PTW.scala
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@ -135,7 +135,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
val l2_refill = RegNext(false.B)
io.dpath.perf.l2miss := false
val (l2_hit, l2_pte) = if (coreParams.nL2TLBEntries == 0) (false.B, Wire(new PTE)) else {
val (l2_hit, l2_valid, l2_pte) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, Wire(new PTE)) else {
val code = new ParityCode
require(isPow2(coreParams.nL2TLBEntries))
val idxBits = log2Ceil(coreParams.nL2TLBEntries)
@ -191,10 +191,10 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
s2_pte.g := s2_g
s2_pte.v := true
(s2_hit, s2_pte)
(s2_hit, s2_valid && s2_valid_bit, s2_pte)
}
io.mem.req.valid := state === s_req && !l2_hit
io.mem.req.valid := state === s_req && !l2_valid
io.mem.req.bits.phys := Bool(true)
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.typ := log2Ceil(xLen/8)
@ -233,7 +233,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
s1_kill := true
count := count + 1
r_pte.ppn := pte_cache_data
}.elsewhen (io.mem.req.ready) {
}.elsewhen (io.mem.req.fire()) {
state := s_wait1
}
}