riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

synchronizers: New chisel ways of cloning type and use simpler lambda function

Browse Source
This commit is contained in:
Megan Wachs
2017-08-30 12:00:14 -07:00
parent bd32f0c122
commit 9dd6c4c32d
2 changed files with 5 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/util/AsyncResetReg.scala
View File

@@ -107,13 +107,3 @@ object AsyncResetReg {
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData=BigInt(0), enable=Bool(true), Some(name))
}
// While this extends from the SynchronizingShiftRegister
// classes, it is just a convenience.
class AsyncResetShiftReg
object AsyncResetShiftRegister(w: Int = 1, depth: Int = 3) extends AbstractSynchronizerReg(w, depth) {
override def desiredName = s"AsyncResetShiftReg_w${w}_d{$sync}"
}
}

10
src/main/scala/util/SynchronizingReg.scala
View File

@@ -29,12 +29,12 @@ abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module
object AbstractSynchronizerReg {
def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
val sync_chain = Module(gen(in.getWidth, sync))
def apply [T <: Chisel.Data](gen: => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
val sync_chain = Module(gen)
name.foreach{ sync_chain.suggestName(_) }
sync_chain.io.d := in.asUInt
(in.chiselCloneType).fromBits(sync_chain.io.q)
sync_chain.io.q.asTypeOf(in)
}
}
@@ -59,7 +59,7 @@ class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Abstract
object AsyncResetSynchronizerShiftReg {
def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new AsyncResetSynchronizerShiftReg(w, sync)},
AbstractSynchronizerReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)},
in, sync, name)
}
@@ -84,6 +84,6 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchroniz
object SynchronizerShiftReg {
def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftReg(w, sync)},
AbstractSynchronizerReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)},
in, sync, name)
}