riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: rename externalBuffers to externalMasterBuffers

This commit is contained in:
Wesley W. Terpstra 2017-09-06 14:40:13 -07:00
parent 4911a7d44f
commit fd8a51a910
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/coreplex/RocketCoreplex.scala
View File

@ -45,19 +45,19 @@ trait HasRocketTiles extends HasSystemBus
val wrapper = crossing match {
case SynchronousCrossing(params) => {
val wrapper = LazyModule(new SyncRocketTile(tp, i)(pWithExtra))
sbus.fromSyncTiles(params, tp.externalBuffers, tp.name) :=* wrapper.masterNode
sbus.fromSyncTiles(params, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.bufferToSlaves
wrapper
}
case AsynchronousCrossing(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(tp, i)(pWithExtra))
sbus.fromAsyncTiles(depth, sync, tp.externalBuffers, tp.name) :=* wrapper.masterNode
sbus.fromAsyncTiles(depth, sync, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name)
wrapper
}
case RationalCrossing(direction) => {
val wrapper = LazyModule(new RationalRocketTile(tp, i)(pWithExtra))
sbus.fromRationalTiles(direction, tp.externalBuffers, tp.name) :=* wrapper.masterNode
sbus.fromRationalTiles(direction, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name)
wrapper
}

2
src/main/scala/tile/RocketTile.scala
View File

@ -20,7 +20,7 @@ case class RocketTileParams(
dataScratchpadBytes: Int = 0,
boundaryBuffers: Boolean = false,
name: Option[String] = Some("tile"),
externalBuffers: Int = 0) extends TileParams {
externalMasterBuffers: Int = 0) extends TileParams {
require(icache.isDefined)
require(dcache.isDefined)
}