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FrontBus: FIFOFixer should not have a buffer between it and Xbar

This commit is contained in:
Wesley W. Terpstra 2017-09-05 16:27:57 -07:00
parent e65f49b89a
commit b74a419bfb
1 changed files with 9 additions and 10 deletions
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19
src/main/scala/coreplex/FrontBus.scala
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@ -19,25 +19,24 @@ case object FrontBusParams extends Field[FrontBusParams]
class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
private val master_buffer = LazyModule(new TLBuffer(params.masterBuffering))
private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
master_fixer.suggestName(s"${busName}_master_TLFIFOFixer")
inwardBufNode :=* master_fixer.node
def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
val (in, out) = bufferChain(addBuffers, name)
inwardBufNode :=* out
in
}
master_buffer.suggestName(s"${busName}_master_TLBuffer")
master_fixer.suggestName(s"${busName}_master_TLFIFOFixer")
master_fixer.node :=* master_buffer.node
inwardNode :=* master_fixer.node
def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
val (in, out) = bufferChain(addBuffers, name)
master_fixer.node :=* out
master_buffer.node :=* out
in
}
def fromSyncFIFOMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
val (in, out) = bufferChain(addBuffers, name)
master_fixer.node :=* out
master_buffer.node :=* out
in
}