Henry Cook
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ebdc0a2692
|
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
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2014-04-10 12:09:52 -07:00 |
|
Andrew Waterman
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c7110c8389
|
Make FPU pipeline depths configurable
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2014-02-28 13:39:59 -08:00 |
|
Yunsup Lee
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97b1841fcf
|
change dcache tag bits to 7
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2014-02-22 22:53:04 -08:00 |
|
Stephen Twigg
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6a02d15c21
|
Merge branch 'master' into hwacha-port
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2014-02-04 17:05:03 -08:00 |
|
Henry Cook
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2c2b3a7678
|
cleanups supporting uncore hierarchy
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2014-01-31 12:07:26 -08:00 |
|
Andrew Waterman
|
0266c1f76a
|
Support retirement width > 1 in CSR file
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2014-01-24 16:37:40 -08:00 |
|
Yunsup Lee
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6bbbf36979
|
push accel/rocket dmem port back to rocket
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2014-01-16 16:01:41 -08:00 |
|
Quan Nguyen
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ebec444ad2
|
Increase tag width for configurable precision in Hwacha
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2013-12-13 03:33:02 -08:00 |
|
Yunsup Lee
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4c56323f6f
|
hookup all memory ports
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2013-11-05 17:12:09 -08:00 |
|
Stephen Twigg
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eae571e371
|
Remove rocc memory simplifye module (Hwacha has its own)
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2013-11-05 15:31:03 -08:00 |
|
Stephen Twigg
|
36b85b8ee2
|
Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached.
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2013-09-25 11:51:10 -07:00 |
|
Andrew Waterman
|
81c752de84
|
Support disabling virtual memory
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2013-09-24 13:58:47 -07:00 |
|
Andrew Waterman
|
f12bbc1e43
|
working RoCC AccumulatorExample
|
2013-09-14 22:34:53 -07:00 |
|
Andrew Waterman
|
d053bdc89f
|
Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
|
2013-09-12 22:34:38 -07:00 |
|
Andrew Waterman
|
d4a0db4575
|
Reflect ISA changes
|
2013-08-24 14:43:55 -07:00 |
|
Henry Cook
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ae02ebd153
|
Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
|
2013-08-15 16:35:27 -07:00 |
|
Henry Cook
|
b570435847
|
Reg standardization
|
2013-08-13 17:50:02 -07:00 |
|
Henry Cook
|
858169917e
|
removed dummy DNCs handled by pruning
|
2013-08-12 22:34:46 -07:00 |
|
Huy Vo
|
387cf0ebe0
|
reset -> resetVal, getReset -> reset
|
2013-08-12 20:51:54 -07:00 |
|
Henry Cook
|
1a9e43aa11
|
initial attempt at upgrade
|
2013-08-12 10:39:11 -07:00 |
|
Henry Cook
|
4eaab214d2
|
Fold uncore constants into TileLinkConfiguration, update coherence API
|
2013-08-02 16:29:51 -07:00 |
|
Henry Cook
|
9abdf4e154
|
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
|
2013-07-23 20:27:58 -07:00 |
|
Henry Cook
|
5c00d0a030
|
new tilelink arbiter type
|
2013-07-09 15:31:46 -07:00 |
|
Henry Cook
|
69b508ff39
|
ported caches and htif to use new tilelink
|
2013-05-21 17:21:04 -07:00 |
|
Henry Cook
|
16113a96ba
|
fixes after merge
|
2013-03-25 19:09:08 -07:00 |
|
Henry Cook
|
95f0a688e9
|
Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
|
2013-03-20 17:37:50 -07:00 |
|
Henry Cook
|
273bd34091
|
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
|
2013-03-20 15:53:36 -07:00 |
|
Henry Cook
|
6d2541aced
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:12:36 -07:00 |
|
Andrew Waterman
|
ea9d0b771e
|
remove aborts; simplify probes
|
2013-03-19 15:29:40 -07:00 |
|
Henry Cook
|
e0361840bd
|
writebacks on release network pass asm tests and bmarks
|
2013-02-28 18:11:40 -08:00 |
|
Henry Cook
|
931cffa749
|
ready signal fix
|
2013-01-27 23:04:35 -08:00 |
|
Henry Cook
|
409b549d3c
|
actually cleared up tile ios
|
2013-01-27 11:27:09 -08:00 |
|
Henry Cook
|
696dd102eb
|
cleans up unconnected tile io pins (networking headers overwritten at top level)
|
2013-01-27 10:59:41 -08:00 |
|
Henry Cook
|
6b00e7ff74
|
New TileLink bundle names
|
2013-01-21 17:18:23 -08:00 |
|
Henry Cook
|
a2fa3fd04d
|
Refactored packet headers/payloads
|
2013-01-15 15:50:37 -08:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
|
2013-01-07 13:41:36 -08:00 |
|
Henry Cook
|
261e14f831
|
Refactored uncore conf
|
2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
|
78868f6075
|
add config option to trade mul/div area for speed
|
2013-01-06 03:47:17 -08:00 |
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Andrew Waterman
|
e9eca6a95d
|
refactor I$ config; remove Top class
|
2012-11-04 16:59:36 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
|
5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
|
Henry Cook
|
88ac5af181
|
Merged consts-as-traits
|
2012-10-16 16:32:35 -07:00 |
|
Andrew Waterman
|
661f8e635b
|
merge I$, ITLB, BTB into Frontend
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
|
8970b635b2
|
improvements to implicit RocketConfiguration parameter
|
2012-10-15 16:29:49 -07:00 |
|
Henry Cook
|
5d2a470215
|
all rocket-specific arbiters in one file and refactored traits slightly
|
2012-10-15 16:05:32 -07:00 |
|
Henry Cook
|
9025d0610c
|
first pass at configuration object passed as implicit parameter
|
2012-10-07 22:37:29 -07:00 |
|
Huy Vo
|
e909093f37
|
factoring out uncore into separate uncore repo
|
2012-10-01 16:08:41 -07:00 |
|
Andrew Waterman
|
f42c6afed2
|
decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
|
2012-07-17 22:55:40 -07:00 |
|
Henry Cook
|
3cdd166153
|
Refactored coherence as member rather than trait. MI and MEI protocols.
|
2012-04-10 00:09:58 -07:00 |
|
Andrew Waterman
|
a09e8d1c55
|
remove I$ prefetcher for now
there's a bug in it, and I don't have time to fix it at the moment.
|
2012-03-27 15:43:56 -07:00 |
|
Andrew Waterman
|
86d56ff67b
|
refactor cpu/i$/d$ into Tile (rather than Top)
|
2012-03-24 16:57:28 -07:00 |
|