Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts: src/core.scala src/ctrl.scala src/dpath_util.scala src/fpu.scala src/nbdcache.scala src/tile.scala
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commit
ae02ebd153
@ -42,7 +42,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
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} else null
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if (conf.vec) {
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val vu = Module(new vu(Reg(next=reset)))
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val vu = Module(new vu(Reg(next=this.reset)))
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val vdtlb = Module(new TLB(8))
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ptw += vdtlb.io.ptw
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@ -278,7 +278,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
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io.host.ipi_rep.ready := Bool(true)
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when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
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when(reset) {
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when(this.reset) {
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reg_status.et := false
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reg_status.ef := false
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reg_status.ev := false
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@ -19,7 +19,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
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if (fastLoadByte) require(fastLoadWord)
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}
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class Tile(_reset: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = _reset) with ClientCoherenceAgent
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
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{
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val memPorts = 2 + confIn.vec
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val dcachePortId = 0
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