fixes after merge
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@ -92,7 +92,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
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val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
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val pcr_coreid = if (conf.ln.nClients == 1) UFix(0) else addr(log2Up(conf.ln.nClients)-1+20,20)
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val pcr_coreid = addr(log2Up(conf.ln.nClients)-1+20+1,20)
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val pcr_wdata = packet_ram(0)
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val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
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@ -55,13 +55,13 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
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io.tilelink.release.bits := dcache.io.mem.release.bits
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io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
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val ioSubBundles = io.tilelink.getClass.getMethods.filter( x =>
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/*val ioSubBundles = io.tilelink.getClass.getMethods.filter( x =>
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classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
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m.invoke(io.tilelink).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] }
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ioSubBundles.foreach{ m =>
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m.bits.header.dst := UFix(0)
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m.bits.header.src := UFix(0)
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}
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}*/
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if (conf.vec) {
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val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)
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