riscv/rocket-chip
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Increase tag width for configurable precision in Hwacha

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This commit is contained in:
Quan Nguyen 2013-12-13 03:33:02 -08:00
parent d450b85483
commit ebec444ad2
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/tile.scala
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@ -12,7 +12,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true)
{
val dcacheReqTagBits = 9 // enforce compliance with require()
val dcacheReqTagBits = 10 // enforce compliance with require() // hue hue hue
val xprlen = 64
val nxpr = 32
val nxprbits = log2Up(nxpr)