all rocket-specific arbiters in one file and refactored traits slightly
This commit is contained in:
Henry Cook
parent
9025d0610c
commit
5d2a470215
@ -2,8 +2,75 @@ package rocket
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import Chisel._
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import Node._
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import Constants._
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import uncore._
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class ioHellaCacheArbiter(n: Int) extends Bundle
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{
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val requestor = Vec(n) { new ioHellaCache() }.flip
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val mem = new ioHellaCache
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}
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class rocketHellaCacheArbiter(n: Int) extends Component
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{
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val io = new ioHellaCacheArbiter(n)
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require(DCACHE_TAG_BITS >= log2Up(n) + CPU_TAG_BITS)
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var req_val = Bool(false)
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var req_rdy = io.mem.req.ready
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for (i <- 0 until n)
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{
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io.requestor(i).req.ready := req_rdy
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req_val = req_val || io.requestor(i).req.valid
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req_rdy = req_rdy && !io.requestor(i).req.valid
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}
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var req_cmd = io.requestor(n-1).req.bits.cmd
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var req_type = io.requestor(n-1).req.bits.typ
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var req_idx = io.requestor(n-1).req.bits.idx
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var req_ppn = io.requestor(n-1).req.bits.ppn
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var req_data = io.requestor(n-1).req.bits.data
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var req_kill = io.requestor(n-1).req.bits.kill
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var req_tag = io.requestor(n-1).req.bits.tag
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for (i <- n-1 to 0 by -1)
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{
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val r = io.requestor(i).req
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req_cmd = Mux(r.valid, r.bits.cmd, req_cmd)
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req_type = Mux(r.valid, r.bits.typ, req_type)
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req_idx = Mux(r.valid, r.bits.idx, req_idx)
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req_ppn = Mux(Reg(r.valid), r.bits.ppn, req_ppn)
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req_data = Mux(Reg(r.valid), r.bits.data, req_data)
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req_kill = Mux(Reg(r.valid), r.bits.kill, req_kill)
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req_tag = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2Up(n))), req_tag)
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}
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io.mem.req.valid := req_val
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io.mem.req.bits.cmd := req_cmd
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io.mem.req.bits.typ := req_type
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io.mem.req.bits.idx := req_idx
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io.mem.req.bits.ppn := req_ppn
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io.mem.req.bits.data := req_data
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io.mem.req.bits.kill := req_kill
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io.mem.req.bits.tag := req_tag
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for (i <- 0 until n)
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{
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val r = io.requestor(i).resp
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val x = io.requestor(i).xcpt
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val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i)
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x.ma.ld := io.mem.xcpt.ma.ld && Reg(io.requestor(i).req.valid)
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x.ma.st := io.mem.xcpt.ma.st && Reg(io.requestor(i).req.valid)
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r.valid := io.mem.resp.valid && tag_hit
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r.bits.miss := io.mem.resp.bits.miss && tag_hit
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r.bits.nack := io.mem.resp.bits.nack && Reg(io.requestor(i).req.valid)
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r.bits.replay := io.mem.resp.bits.replay && tag_hit
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r.bits.data := io.mem.resp.bits.data
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r.bits.data_subword := io.mem.resp.bits.data_subword
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r.bits.typ := io.mem.resp.bits.typ
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r.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n))
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}
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}
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class ioUncachedRequestor extends Bundle {
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val xact_init = (new FIFOIO) { new TransactionInit }
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val xact_abort = (new FIFOIO) { new TransactionAbort }.flip
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@ -5,7 +5,7 @@ import Chisel._
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import scala.math._
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abstract trait MulticoreConstants {
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val NTILES: Int = 1
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val NTILES: Int
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val TILE_ID_BITS = log2Up(NTILES)+1
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}
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@ -19,19 +19,46 @@ trait UncoreConstants {
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val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS)
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}
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trait HTIFConstants {
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val HTIF_WIDTH = 16
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val MEM_BACKUP_WIDTH = HTIF_WIDTH
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trait TileLinkTypeConstants {
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val X_INIT_TYPE_MAX_BITS = 2
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val X_REP_TYPE_MAX_BITS = 3
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val P_REQ_TYPE_MAX_BITS = 2
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val P_REP_TYPE_MAX_BITS = 3
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}
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abstract trait TileConfigConstants extends UncoreConstants with MulticoreConstants {
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val HAVE_RVC: Boolean
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val HAVE_FPU: Boolean
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val HAVE_VEC: Boolean
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def FPU_N = UFix(0, 1)
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def FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N
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def VEC_N = UFix(0, 1);
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def VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N
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trait TileLinkSizeConstants extends
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RocketDcacheConstants with
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TileLinkTypeConstants
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{
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val TILE_XACT_ID_BITS = log2Up(NMSHR)+3
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val X_INIT_WRITE_MASK_BITS = OFFSET_BITS
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val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS)
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val X_INIT_ATOMIC_OP_BITS = 4
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}
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trait HTIFConstants {
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val HTIF_WIDTH = 16
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}
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trait MemoryInterfaceConstants extends
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HTIFConstants with
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UncoreConstants with
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TileLinkSizeConstants
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{
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val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)
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val MEM_DATA_BITS = 128
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val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
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val MEM_BACKUP_WIDTH = HTIF_WIDTH
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}
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abstract trait TileConfigConstants {
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def HAVE_RVC: Boolean
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def HAVE_FPU: Boolean
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def HAVE_VEC: Boolean
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val FPU_N = UFix(0, 1)
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val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N
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val VEC_N = UFix(0, 1);
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val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N
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}
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trait ScalarOpConstants {
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@ -202,39 +229,21 @@ trait AddressConstants {
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val PERM_BITS = 6;
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}
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abstract trait RocketDcacheConstants extends TileConfigConstants with AddressConstants {
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val DCACHE_PORTS = 3
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abstract trait RocketDcacheConstants extends ArbiterConstants with AddressConstants {
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val CPU_DATA_BITS = 64;
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val CPU_TAG_BITS = 9;
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val DCACHE_TAG_BITS = log2Up(DCACHE_PORTS) + CPU_TAG_BITS
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val OFFSET_BITS = 6; // log2(cache line size in bytes)
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val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
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val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses
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val NRPQ = 16; // number of secondary misses
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val NSDQ = 17; // number of secondary stores/AMOs
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val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
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val OFFSET_BITS = 6; // log2(cache line size in bytes)
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val IDX_BITS = 7;
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val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS;
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val NWAYS = 4
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require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
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}
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trait TileLinkSizeConstants extends RocketDcacheConstants {
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val TILE_XACT_ID_BITS = log2Up(NMSHR)+3
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val X_INIT_TYPE_MAX_BITS = 2
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val X_INIT_WRITE_MASK_BITS = OFFSET_BITS
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val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS)
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val X_INIT_ATOMIC_OP_BITS = 4
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val X_REP_TYPE_MAX_BITS = 3
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val P_REQ_TYPE_MAX_BITS = 2
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val P_REP_TYPE_MAX_BITS = 3
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}
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trait MemoryInterfaceConstants extends UncoreConstants with TileLinkSizeConstants {
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val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)
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val MEM_DATA_BITS = 128
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val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
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}
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trait TLBConstants {
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val DTLB_ENTRIES = 16
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val ITLB_ENTRIES = 8;
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@ -266,12 +275,19 @@ trait VectorOpConstants {
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val VIMM2_X = UFix(0, 1)
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}
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trait ArbiterConstants {
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abstract trait ArbiterConstants extends TileConfigConstants {
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val DTLB_PORTS = 3
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val DTLB_CPU = 0
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val DTLB_VEC = 1
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val DTLB_VPF = 2
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val DMEM_CPU = 0
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val DMEM_PTW = 1
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val DMEM_VU = 2
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val DCACHE_PORTS = 3
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val DCACHE_CPU = 0
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val DCACHE_PTW = 1
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val DCACHE_VU = 2
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val DMEM_PORTS = if (HAVE_VEC) 3 else 2
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val DMEM_DCACHE = 0
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val DMEM_ICACHE = 1
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val DMEM_VICACHE = 2
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}
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@ -30,8 +30,8 @@ class rocketProc()(implicit conf: Configuration) extends Component
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{
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vu = new vu()
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// cpu, vector prefetch, and vector use the DTLB
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val dtlbarb = new RRArbiter(3)({new ioDTLB_CPU_req_bundle()})
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val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(3)))
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val dtlbarb = new RRArbiter(DTLB_PORTS)({new ioDTLB_CPU_req_bundle()})
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val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(DTLB_PORTS)))
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when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
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// tlb respones come out a cycle later
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@ -86,15 +86,15 @@ class rocketProc()(implicit conf: Configuration) extends Component
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dtlb.io.invalidate := dpath.io.ptbr_wen
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dtlb.io.status := dpath.io.ctrl.status
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arb.io.requestor(DMEM_CPU).req.bits.ppn := dtlb.io.cpu_resp.ppn
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ctrl.io.dmem.req.ready := dtlb.io.cpu_req.ready && arb.io.requestor(DMEM_CPU).req.ready
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arb.io.requestor(DCACHE_CPU).req.bits.ppn := dtlb.io.cpu_resp.ppn
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ctrl.io.dmem.req.ready := dtlb.io.cpu_req.ready && arb.io.requestor(DCACHE_CPU).req.ready
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// connect page table walker to TLBs, page table base register (from PCR)
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// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
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ptw.io.requestor(0) <> itlb.io.ptw
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ptw.io.requestor(1) <> dtlb.io.ptw
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ptw.io.ptbr := dpath.io.ptbr;
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arb.io.requestor(DMEM_PTW) <> ptw.io.mem
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arb.io.requestor(DCACHE_PTW) <> ptw.io.mem
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arb.io.mem <> io.dmem
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ctrl.io.dpath <> dpath.io.ctrl;
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@ -119,17 +119,17 @@ class rocketProc()(implicit conf: Configuration) extends Component
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// connect arbiter to ctrl+dpath+DTLB
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//TODO: views on nested bundles?
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arb.io.requestor(DMEM_CPU).resp <> ctrl.io.dmem.resp
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arb.io.requestor(DMEM_CPU).xcpt <> ctrl.io.dmem.xcpt
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arb.io.requestor(DMEM_CPU).resp <> dpath.io.dmem.resp
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arb.io.requestor(DMEM_CPU).req.valid := ctrl.io.dmem.req.valid
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ctrl.io.dmem.req.ready := arb.io.requestor(DMEM_CPU).req.ready
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arb.io.requestor(DMEM_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill
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arb.io.requestor(DMEM_CPU).req.bits.cmd := ctrl.io.dmem.req.bits.cmd
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arb.io.requestor(DMEM_CPU).req.bits.typ := ctrl.io.dmem.req.bits.typ
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arb.io.requestor(DMEM_CPU).req.bits.idx := dpath.io.dmem.req.bits.idx
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arb.io.requestor(DMEM_CPU).req.bits.tag := dpath.io.dmem.req.bits.tag
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arb.io.requestor(DMEM_CPU).req.bits.data := dpath.io.dmem.req.bits.data
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arb.io.requestor(DCACHE_CPU).resp <> ctrl.io.dmem.resp
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arb.io.requestor(DCACHE_CPU).xcpt <> ctrl.io.dmem.xcpt
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arb.io.requestor(DCACHE_CPU).resp <> dpath.io.dmem.resp
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arb.io.requestor(DCACHE_CPU).req.valid := ctrl.io.dmem.req.valid
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ctrl.io.dmem.req.ready := arb.io.requestor(DCACHE_CPU).req.ready
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arb.io.requestor(DCACHE_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill
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arb.io.requestor(DCACHE_CPU).req.bits.cmd := ctrl.io.dmem.req.bits.cmd
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arb.io.requestor(DCACHE_CPU).req.bits.typ := ctrl.io.dmem.req.bits.typ
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arb.io.requestor(DCACHE_CPU).req.bits.idx := dpath.io.dmem.req.bits.idx
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arb.io.requestor(DCACHE_CPU).req.bits.tag := dpath.io.dmem.req.bits.tag
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arb.io.requestor(DCACHE_CPU).req.bits.data := dpath.io.dmem.req.bits.data
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var fpu: rocketFPU = null
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if (HAVE_FPU)
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@ -217,21 +217,21 @@ class rocketProc()(implicit conf: Configuration) extends Component
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storegen.io.typ := vu.io.dmem_req.bits.typ
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storegen.io.din := vu.io.dmem_req.bits.data
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arb.io.requestor(DMEM_VU).req.valid := vu.io.dmem_req.valid
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arb.io.requestor(DMEM_VU).req.bits.kill := vu.io.dmem_req.bits.kill
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arb.io.requestor(DMEM_VU).req.bits.cmd := vu.io.dmem_req.bits.cmd
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arb.io.requestor(DMEM_VU).req.bits.typ := vu.io.dmem_req.bits.typ
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arb.io.requestor(DMEM_VU).req.bits.idx := vu.io.dmem_req.bits.idx
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arb.io.requestor(DMEM_VU).req.bits.ppn := Reg(vu.io.dmem_req.bits.ppn)
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arb.io.requestor(DMEM_VU).req.bits.data := Reg(storegen.io.dout)
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arb.io.requestor(DMEM_VU).req.bits.tag := vu.io.dmem_req.bits.tag
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arb.io.requestor(DCACHE_VU).req.valid := vu.io.dmem_req.valid
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arb.io.requestor(DCACHE_VU).req.bits.kill := vu.io.dmem_req.bits.kill
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arb.io.requestor(DCACHE_VU).req.bits.cmd := vu.io.dmem_req.bits.cmd
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arb.io.requestor(DCACHE_VU).req.bits.typ := vu.io.dmem_req.bits.typ
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arb.io.requestor(DCACHE_VU).req.bits.idx := vu.io.dmem_req.bits.idx
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arb.io.requestor(DCACHE_VU).req.bits.ppn := Reg(vu.io.dmem_req.bits.ppn)
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arb.io.requestor(DCACHE_VU).req.bits.data := Reg(storegen.io.dout)
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arb.io.requestor(DCACHE_VU).req.bits.tag := vu.io.dmem_req.bits.tag
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vu.io.dmem_req.ready := arb.io.requestor(DMEM_VU).req.ready
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vu.io.dmem_resp.valid := Reg(arb.io.requestor(DMEM_VU).resp.valid)
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vu.io.dmem_resp.bits.nack := arb.io.requestor(DMEM_VU).resp.bits.nack
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vu.io.dmem_resp.bits.data := arb.io.requestor(DMEM_VU).resp.bits.data_subword
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vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DMEM_VU).resp.bits.tag)
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vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DMEM_VU).resp.bits.typ)
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vu.io.dmem_req.ready := arb.io.requestor(DCACHE_VU).req.ready
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vu.io.dmem_resp.valid := Reg(arb.io.requestor(DCACHE_VU).resp.valid)
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vu.io.dmem_resp.bits.nack := arb.io.requestor(DCACHE_VU).resp.bits.nack
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vu.io.dmem_resp.bits.data := arb.io.requestor(DCACHE_VU).resp.bits.data_subword
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vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DCACHE_VU).resp.bits.tag)
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vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DCACHE_VU).resp.bits.typ)
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// share vector integer multiplier with rocket
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dpath.io.vec_imul_req <> vu.io.cp_imul_req
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@ -243,7 +243,7 @@ class rocketProc()(implicit conf: Configuration) extends Component
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}
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else
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{
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arb.io.requestor(DMEM_VU).req.valid := Bool(false)
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arb.io.requestor(DCACHE_VU).req.valid := Bool(false)
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if (HAVE_FPU)
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{
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fpu.io.sfma.valid := Bool(false)
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@ -6,20 +6,19 @@ import scala.math._
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//TODO: When compiler bug SI-5604 is fixed in 2.10, change object Constants to
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// package object rocket and remove import Constants._'s from other files
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object Constants extends HTIFConstants with
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object Constants extends
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ScalarOpConstants with
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MemoryOpConstants with
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PCRConstants with
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InterruptConstants with
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AddressConstants with
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ArbiterConstants with
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VectorOpConstants with
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TLBConstants with
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ScalarOpConstants with
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MemoryInterfaceConstants
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{
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val HAVE_RVC = false
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val HAVE_FPU = true
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val HAVE_VEC = true
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def HAVE_RVC = false
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def HAVE_FPU = true
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def HAVE_VEC = true
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val MAX_THREADS =
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hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
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@ -5,72 +5,6 @@ import Node._
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import Constants._
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import scala.math._
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class ioHellaCacheArbiter(n: Int) extends Bundle
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{
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val requestor = Vec(n) { new ioHellaCache() }.flip
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val mem = new ioHellaCache
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}
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class rocketHellaCacheArbiter(n: Int) extends Component
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{
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val io = new ioHellaCacheArbiter(n)
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require(DCACHE_TAG_BITS >= log2Up(n) + CPU_TAG_BITS)
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var req_val = Bool(false)
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var req_rdy = io.mem.req.ready
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for (i <- 0 until n)
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{
|
||||
io.requestor(i).req.ready := req_rdy
|
||||
req_val = req_val || io.requestor(i).req.valid
|
||||
req_rdy = req_rdy && !io.requestor(i).req.valid
|
||||
}
|
||||
|
||||
var req_cmd = io.requestor(n-1).req.bits.cmd
|
||||
var req_type = io.requestor(n-1).req.bits.typ
|
||||
var req_idx = io.requestor(n-1).req.bits.idx
|
||||
var req_ppn = io.requestor(n-1).req.bits.ppn
|
||||
var req_data = io.requestor(n-1).req.bits.data
|
||||
var req_kill = io.requestor(n-1).req.bits.kill
|
||||
var req_tag = io.requestor(n-1).req.bits.tag
|
||||
for (i <- n-1 to 0 by -1)
|
||||
{
|
||||
val r = io.requestor(i).req
|
||||
req_cmd = Mux(r.valid, r.bits.cmd, req_cmd)
|
||||
req_type = Mux(r.valid, r.bits.typ, req_type)
|
||||
req_idx = Mux(r.valid, r.bits.idx, req_idx)
|
||||
req_ppn = Mux(Reg(r.valid), r.bits.ppn, req_ppn)
|
||||
req_data = Mux(Reg(r.valid), r.bits.data, req_data)
|
||||
req_kill = Mux(Reg(r.valid), r.bits.kill, req_kill)
|
||||
req_tag = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2Up(n))), req_tag)
|
||||
}
|
||||
|
||||
io.mem.req.valid := req_val
|
||||
io.mem.req.bits.cmd := req_cmd
|
||||
io.mem.req.bits.typ := req_type
|
||||
io.mem.req.bits.idx := req_idx
|
||||
io.mem.req.bits.ppn := req_ppn
|
||||
io.mem.req.bits.data := req_data
|
||||
io.mem.req.bits.kill := req_kill
|
||||
io.mem.req.bits.tag := req_tag
|
||||
|
||||
for (i <- 0 until n)
|
||||
{
|
||||
val r = io.requestor(i).resp
|
||||
val x = io.requestor(i).xcpt
|
||||
val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i)
|
||||
x.ma.ld := io.mem.xcpt.ma.ld && Reg(io.requestor(i).req.valid)
|
||||
x.ma.st := io.mem.xcpt.ma.st && Reg(io.requestor(i).req.valid)
|
||||
r.valid := io.mem.resp.valid && tag_hit
|
||||
r.bits.miss := io.mem.resp.bits.miss && tag_hit
|
||||
r.bits.nack := io.mem.resp.bits.nack && Reg(io.requestor(i).req.valid)
|
||||
r.bits.replay := io.mem.resp.bits.replay && tag_hit
|
||||
r.bits.data := io.mem.resp.bits.data
|
||||
r.bits.data_subword := io.mem.resp.bits.data_subword
|
||||
r.bits.typ := io.mem.resp.bits.typ
|
||||
r.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n))
|
||||
}
|
||||
}
|
||||
|
||||
class ioPTW(n: Int) extends Bundle
|
||||
{
|
||||
val requestor = Vec(n) { new ioTLB_PTW }.flip
|
||||
|
||||
@ -16,9 +16,9 @@ class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Compo
|
||||
val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
|
||||
val dcache = new HellaCache
|
||||
|
||||
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
|
||||
arbiter.io.requestor(0) <> dcache.io.mem
|
||||
arbiter.io.requestor(1) <> icache.io.mem
|
||||
val arbiter = new rocketMemArbiter(DMEM_PORTS)
|
||||
arbiter.io.requestor(DMEM_DCACHE) <> dcache.io.mem
|
||||
arbiter.io.requestor(DMEM_ICACHE) <> icache.io.mem
|
||||
|
||||
io.tilelink.xact_init <> arbiter.io.mem.xact_init
|
||||
io.tilelink.xact_init_data <> dcache.io.mem.xact_init_data
|
||||
@ -32,7 +32,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Compo
|
||||
if (HAVE_VEC)
|
||||
{
|
||||
val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
|
||||
arbiter.io.requestor(2) <> vicache.io.mem
|
||||
arbiter.io.requestor(DMEM_VICACHE) <> vicache.io.mem
|
||||
cpu.io.vimem <> vicache.io.cpu
|
||||
}
|
||||
|
||||
|
||||
@ -6,8 +6,8 @@ import Constants._
|
||||
import uncore._
|
||||
import collection.mutable.ArrayBuffer
|
||||
|
||||
object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants {
|
||||
// val NTILES = 1
|
||||
object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants with rocket.constants.MulticoreConstants {
|
||||
val NTILES = 1
|
||||
val ENABLE_SHARING = true
|
||||
val ENABLE_CLEAN_EXCLUSIVE = true
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user