nTiles -> nClients in LogicalNetworkConfig
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@ -8,7 +8,7 @@ import Util._
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class RocketIO(implicit conf: RocketConfiguration) extends Bundle
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{
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val host = new HTIFIO(conf.lnConf.nTiles)
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val host = new HTIFIO(conf.lnConf.nClients)
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val imem = new CPUFrontendIO()(conf.icache)
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val vimem = new CPUFrontendIO()(conf.icache)
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val dmem = new HellaCacheIO()(conf.dcache)
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@ -10,7 +10,7 @@ import hwacha._
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class Datapath(implicit conf: RocketConfiguration) extends Component
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{
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val io = new Bundle {
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val host = new HTIFIO(conf.lnConf.nTiles)
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val host = new HTIFIO(conf.lnConf.nClients)
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val ctrl = (new CtrlDpathIO).flip
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val dmem = new HellaCacheIO()(conf.dcache)
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val ptw = (new DatapathPTWIO).flip
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@ -104,7 +104,7 @@ object PCR
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class PCR(implicit conf: RocketConfiguration) extends Component
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{
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val io = new Bundle {
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val host = new HTIFIO(conf.lnConf.nTiles)
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val host = new HTIFIO(conf.lnConf.nClients)
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val r = new ioReadPort(conf.nxpr, conf.xprlen)
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val w = new ioWritePort(conf.nxpr, conf.xprlen)
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@ -41,7 +41,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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implicit val lnConf = conf.ln
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val io = new Bundle {
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val host = new HostIO(w)
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val cpu = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles).flip }
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val cpu = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients).flip }
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val mem = new TileLinkIO()(conf.ln)
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}
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@ -82,7 +82,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
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val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
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val pcr_coreid = if (conf.ln.nTiles == 1) UFix(0) else addr(20+log2Up(conf.ln.nTiles),20)
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val pcr_coreid = if (conf.ln.nClients == 1) UFix(0) else addr(20+log2Up(conf.ln.nClients),20)
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val pcr_wdata = packet_ram(0)
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val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
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@ -182,19 +182,19 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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io.mem.release.valid := Bool(false)
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io.mem.release_data.valid := Bool(false)
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io.mem.acquire.bits.header.src := UFix(conf.ln.nTiles)
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io.mem.acquire.bits.header.src := UFix(conf.ln.nClients)
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io.mem.acquire.bits.header.dst := UFix(0)
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io.mem.acquire_data.bits.header.src := UFix(conf.ln.nTiles)
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io.mem.acquire_data.bits.header.src := UFix(conf.ln.nClients)
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io.mem.acquire_data.bits.header.dst := UFix(0)
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io.mem.release.bits.header.src := UFix(conf.ln.nTiles)
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io.mem.release.bits.header.src := UFix(conf.ln.nClients)
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io.mem.release.bits.header.dst := UFix(0)
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io.mem.release_data.bits.header.src := UFix(conf.ln.nTiles)
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io.mem.release_data.bits.header.src := UFix(conf.ln.nClients)
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io.mem.release_data.bits.header.dst := UFix(0)
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io.mem.grant_ack.bits.header.src := UFix(conf.ln.nTiles)
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io.mem.grant_ack.bits.header.src := UFix(conf.ln.nClients)
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io.mem.grant_ack.bits.header.dst := UFix(0)
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val pcrReadData = Vec(conf.ln.nTiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
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for (i <- 0 until conf.ln.nTiles) {
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val pcrReadData = Vec(conf.ln.nClients) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
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for (i <- 0 until conf.ln.nClients) {
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val my_reset = Reg(resetVal = Bool(true))
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val my_ipi = Reg(resetVal = Bool(false))
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@ -211,7 +211,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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}
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cpu.ipi_rep.valid := my_ipi
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cpu.ipi_req.ready := Bool(true)
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for (j <- 0 until conf.ln.nTiles) {
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for (j <- 0 until conf.ln.nClients) {
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when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
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my_ipi := Bool(true)
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}
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@ -31,7 +31,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
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val io = new Bundle {
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val tilelink = new TileLinkIO
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val host = new HTIFIO(lnConf.nTiles)
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val host = new HTIFIO(lnConf.nClients)
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}
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val core = new Core
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