riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

change dcache tag bits to 7

Browse Source
This commit is contained in:
Yunsup Lee 2014-02-22 22:53:04 -08:00
parent 8e3ca609f7
commit 97b1841fcf
2 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
rocket/src/main/scala/dpath.scala
View File

@ -180,6 +180,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
require(io.dmem.req.bits.tag.getWidth >= 6)
require(conf.dcacheReqTagBits >= 6)
// processor control regfile read
val pcr = Module(new CSRFile)

2
rocket/src/main/scala/tile.scala
View File

@ -13,7 +13,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true)
{
val dcacheReqTagBits = 10 // enforce compliance with require() // hue hue hue
val dcacheReqTagBits = 7 // enforce compliance with require()
val xprlen = 64
val nxpr = 32
val nxprbits = log2Up(nxpr)