riscv/rocket-chip
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Support disabling virtual memory

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This commit is contained in:
Andrew Waterman
2013-09-24 13:58:23 -07:00
parent adc386f889
commit 81c752de84
2 changed files with 2 additions and 0 deletions
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1
rocket/src/main/scala/dpath_util.scala
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@@ -242,6 +242,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
reg_status.s64 := true
reg_status.u64 := true
reg_status.zero := 0
if (!conf.vm) reg_status.vm := false
if (conf.rocc.isEmpty) reg_status.er := false
if (!conf.fpu) reg_status.ef := false
}

1
rocket/src/main/scala/tile.scala
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@@ -7,6 +7,7 @@ import Util._
case class RocketConfiguration(tl: TileLinkConfiguration,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None,
vm: Boolean = true,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true)