67 lines
2.5 KiB
Scala
67 lines
2.5 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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import uncore._
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import Util._
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case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: CoherencePolicyWithUncached,
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icache: ICacheConfig, dcache: DCacheConfig,
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fpu: Boolean, vec: Boolean,
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fastLoadWord: Boolean = true,
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fastLoadByte: Boolean = false,
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fastMulDiv: Boolean = true)
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{
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val dcacheReqTagBits = 9 // enforce compliance with require()
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val xprlen = 64
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val nxpr = 32
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val nxprbits = log2Up(nxpr)
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val rvc = false
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if (fastLoadByte) require(fastLoadWord)
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}
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent
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{
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val memPorts = 2 + confIn.vec
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val dcachePortID = 0
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implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
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implicit val lnConf = confIn.lnConf
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implicit val conf = confIn.copy(dcache = dcConf)
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val io = new Bundle {
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val tilelink = new TileLinkIO
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val host = new HTIFIO(lnConf.nTiles)
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}
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val core = new Core
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val icache = new Frontend()(confIn.icache, lnConf)
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val dcache = new HellaCache
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val arbiter = new MemArbiter(memPorts)
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arbiter.io.requestor(dcachePortID) <> dcache.io.mem
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arbiter.io.requestor(1) <> icache.io.mem
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io.tilelink.acquire <> arbiter.io.mem.acquire
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io.tilelink.acquire_data <> dcache.io.mem.acquire_data
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arbiter.io.mem.abort <> io.tilelink.abort
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arbiter.io.mem.grant <> io.tilelink.grant
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io.tilelink.grant_ack <> arbiter.io.mem.grant_ack
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dcache.io.mem.probe <> io.tilelink.probe
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io.tilelink.release_data <> dcache.io.mem.release_data
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io.tilelink.release.valid := dcache.io.mem.release.valid
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dcache.io.mem.release.ready := io.tilelink.release.ready
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io.tilelink.release.bits := dcache.io.mem.release.bits
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io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortID, log2Up(memPorts))) // Mimic client id extension done by MemArbiter for Acquires from either cache)
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if (conf.vec) {
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val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)
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arbiter.io.requestor(2) <> vicache.io.mem
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core.io.vimem <> vicache.io.cpu
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}
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core.io.host <> io.host
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core.io.imem <> icache.io.cpu
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core.io.dmem <> dcache.io.cpu
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}
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