75 lines
2.8 KiB
Scala
75 lines
2.8 KiB
Scala
package rocket
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import Chisel._
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import uncore._
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import Util._
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case class RocketConfiguration(tl: TileLinkConfiguration,
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icache: ICacheConfig, dcache: DCacheConfig,
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fpu: Boolean, vec: Boolean,
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fastLoadWord: Boolean = true,
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fastLoadByte: Boolean = false,
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fastMulDiv: Boolean = true)
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{
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val dcacheReqTagBits = 9 // enforce compliance with require()
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val xprlen = 64
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val nxpr = 32
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val nxprbits = log2Up(nxpr)
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val rvc = false
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if (fastLoadByte) require(fastLoadWord)
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}
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
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{
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val memPorts = 2 + confIn.vec
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val dcachePortId = 0
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val icachePortId = 1
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val vicachePortId = 2
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implicit val tlConf = confIn.tl
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implicit val lnConf = confIn.tl.ln
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implicit val icConf = confIn.icache
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implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
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implicit val conf = confIn.copy(dcache = dcConf)
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val io = new Bundle {
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val tilelink = new TileLinkIO
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val host = new HTIFIO(lnConf.nClients)
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}
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val core = Module(new Core)
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val icache = Module(new Frontend)
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val dcache = Module(new HellaCache)
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val arbiter = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts))
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arbiter.io.in(dcachePortId) <> dcache.io.mem
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arbiter.io.in(icachePortId) <> icache.io.mem
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io.tilelink.acquire <> arbiter.io.out.acquire
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arbiter.io.out.grant <> io.tilelink.grant
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io.tilelink.grant_ack <> arbiter.io.out.grant_ack
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dcache.io.mem.probe <> io.tilelink.probe
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io.tilelink.release.data <> dcache.io.mem.release.data
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io.tilelink.release.meta.valid := dcache.io.mem.release.meta.valid
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dcache.io.mem.release.meta.ready := io.tilelink.release.meta.ready
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io.tilelink.release.meta.bits := dcache.io.mem.release.meta.bits
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io.tilelink.release.meta.bits.payload.client_xact_id := Cat(dcache.io.mem.release.meta.bits.payload.client_xact_id, UInt(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
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/*val ioSubBundles = io.tilelink.getClass.getMethods.filter( x =>
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classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
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m.invoke(io.tilelink).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] }
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ioSubBundles.foreach{ m =>
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m.bits.header.dst := UInt(0)
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m.bits.header.src := UInt(0)
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}*/
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if (conf.vec) {
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val vicache = Module(new Frontend()(ICacheConfig(128, 1), tlConf)) // 128 sets x 1 ways (8KB)
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arbiter.io.in(vicachePortId) <> vicache.io.mem
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core.io.vimem <> vicache.io.cpu
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}
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core.io.host <> io.host
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core.io.imem <> icache.io.cpu
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core.io.dmem <> dcache.io.cpu
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}
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