Yunsup Lee
e28a551368
refactor code related to vector exceptions
...
- revisied interfaces
- new instructions
2012-03-03 15:15:00 -08:00
Yunsup Lee
1054cec087
add vec countq interface
2012-03-02 00:43:32 -08:00
Yunsup Lee
8678b3d70c
clean up ioDecoupled/ioPipe interface
2012-03-01 20:48:46 -08:00
Yunsup Lee
bfd0ae125e
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
2012-02-26 23:46:51 -08:00
Andrew Waterman
e12b9eae93
remove ext_mem interface
...
hindsight is 20/20
2012-02-26 18:53:39 -08:00
Andrew Waterman
2d04664a98
simplify cpu-cache interface
2012-02-26 18:26:29 -08:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Yunsup Lee
946e0c6e4e
add vector exception infrastructure
2012-02-25 16:37:56 -08:00
Yunsup Lee
3839e3a318
massive refactoring of vector constants
2012-02-25 15:55:36 -08:00
Yunsup Lee
a1600d95db
fix bug related to waddr and wdata in wb stage
...
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
2012-02-25 12:21:10 -08:00
Andrew Waterman
4121fb178c
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-24 19:22:35 -08:00
Andrew Waterman
f939088be1
move datapath control signals into control unit
...
because that's where control signals go
2012-02-23 16:52:52 -08:00
Andrew Waterman
cfd79c731b
add resp_type to ext_mem interface
2012-02-21 17:42:00 -08:00
Andrew Waterman
7034c9be65
new htif protocol and implementation
...
You must update your fesvr and isasim!
2012-02-19 23:15:45 -08:00
Yunsup Lee
32bdf5098a
refactor vector control logic & datapath in the rocket core
2012-02-15 13:30:22 -08:00
Yunsup Lee
6bdf9dc513
hwacha integration: now it compiles correctly!
2012-02-14 23:34:57 -08:00
Andrew Waterman
069037ff3a
add FP recoding
2012-02-12 23:31:50 -08:00
Andrew Waterman
08b6517a23
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-12 20:12:53 -08:00
Andrew Waterman
9bb1558a34
WIP on FPU
2012-02-12 04:36:01 -08:00
Andrew Waterman
50a283d311
move store data generation into EX stage
...
doing so removes it from the critical path of FP store unrecoding.
2012-02-12 01:35:55 -08:00
Andrew Waterman
725190d0ee
update to new chisel
2012-02-11 17:20:33 -08:00
Andrew Waterman
f8b937d590
fix 32-bit divider bug
...
thanks, torture!
also, tidied up the code a bit.
2012-02-09 03:47:59 -08:00
Yunsup Lee
f47d888feb
vvcfgivl and vsetvl works
2012-02-09 02:35:21 -08:00
Andrew Waterman
92493ad153
fix mul/div kill bug
...
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
2012-02-09 02:26:03 -08:00
Andrew Waterman
128ec567ed
make BTB fully associative; don't use it for JALR
...
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
2012-02-09 01:34:00 -08:00
Yunsup Lee
fcc8081c4d
hook up the vector command queue
2012-02-09 01:28:16 -08:00
Andrew Waterman
8b6b0f5367
add external memory request interface for vec unit
2012-02-08 22:30:45 -08:00
Yunsup Lee
9285a52f25
initial vu integration
2012-02-08 21:43:45 -08:00
Andrew Waterman
b3f6f9a5fd
fix BTB misprediction check for negative addresses
...
also index BTB with PC, not PC+4
2012-02-08 15:05:28 -08:00
Andrew Waterman
e9da2cf66a
improve id/ex datapath
...
move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
Andrew Waterman
d471a8b2da
arbitrate for LLFU writebacks in MEM stage
2012-02-08 04:21:05 -08:00
Andrew Waterman
5403d069e9
add fp loads/stores
2012-02-07 23:54:25 -08:00
Andrew Waterman
fde8e3b696
clean up bypassing/hazard checking a bit
2012-02-06 17:26:45 -08:00
Andrew Waterman
99a959e6b1
remove pc+4 piperegs and add new ex pc+4 adder
2012-02-02 13:33:27 -08:00
Andrew Waterman
b1bbf56b74
clean up wb->id bypass
2012-02-01 16:41:18 -08:00
Andrew Waterman
f1c355e3cd
check pc/effective address sign extension
2012-01-24 00:15:17 -08:00
Henry Cook
8766438bb9
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
2012-01-23 17:09:23 -08:00
Henry Cook
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
Andrew Waterman
0369b05deb
move replays to writeback stage
2012-01-17 21:12:31 -08:00
Andrew Waterman
bcb55e581a
remove host.start signal, use reset instead
2012-01-11 17:49:32 -08:00
Andrew Waterman
20aee36c96
move PCR writes to WB stage
2012-01-02 15:42:39 -08:00
Andrew Waterman
3045b33460
remove second RF write port
...
load miss writebacks are treated like mul/div now.
2012-01-02 02:51:30 -08:00
Andrew Waterman
ffe23a1ee8
fix WAW hazard handling
2012-01-02 00:25:11 -08:00
Andrew Waterman
eb657dd250
reduce superfluous replays
...
we only replay after a cache miss if we mis-scheduled the use of a load.
2012-01-01 21:28:38 -08:00
Andrew Waterman
efc623cc36
validate BTB address and use BTB for J/JAL/JR/JALR
...
even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
2012-01-01 17:04:14 -08:00
Andrew Waterman
2f8fcebea0
remove datapath register resets resets
2012-01-01 16:09:40 -08:00
Andrew Waterman
733fc8e65e
booth multiplier
2011-12-20 03:49:07 -08:00
Andrew Waterman
b5a8b6dc73
fix divider for RV32
2011-12-19 16:57:53 -08:00
Andrew Waterman
bcceb08373
add dummy mul_rdy signal
2011-12-17 07:30:47 -08:00
Andrew Waterman
82700cad72
fix multiplier for rv32
2011-12-17 07:20:00 -08:00
Andrew Waterman
56c4f44c2a
hellacache returns!
...
but AMOs are unimplemented.
2011-12-12 06:49:39 -08:00
Andrew Waterman
ce201559f3
Support cache->cpu nacks one cycle after request
2011-12-10 00:42:09 -08:00
Andrew Waterman
c01e1f1cef
Don't replay from EX stage.
...
EX replays are now handled from MEM. We may move them to WB.
2011-12-09 19:42:58 -08:00
Rimas Avizienis
e70b41241c
changed branch addr generation to get it off critical path
2011-12-02 01:56:17 -08:00
Rimas Avizienis
da2fdf4f85
fixed console i/o
2011-11-30 22:51:59 -08:00
Rimas Avizienis
bc44572d99
bugfixes due to new hcl jar file
2011-11-30 21:54:55 -08:00
Rimas Avizienis
11f0e3daf4
more cleanup
2011-11-18 00:17:30 -08:00
Rimas Avizienis
c42d8149b7
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
2011-11-17 23:50:45 -08:00
Rimas Avizienis
80b4253318
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
2011-11-16 02:04:28 -08:00
Rimas Avizienis
886857fa47
writes of PC weren't being sign extended
2011-11-15 18:07:36 -08:00
Rimas Avizienis
48cec01710
updated riscv-bmarks and riscv-tests to build with new toolchain
2011-11-15 00:11:22 -08:00
Rimas Avizienis
cd6e463320
added ei and di instructions
2011-11-14 13:48:49 -08:00
Rimas Avizienis
b791010bb1
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 04:13:13 -08:00
Rimas Avizienis
890bfa7c48
added IPIs and timer interrupts
2011-11-14 03:24:02 -08:00
Rimas Avizienis
5b29765917
synced up with supervisor mode state in latest ISA simulator
2011-11-14 01:37:20 -08:00
Rimas Avizienis
44419511b7
timer interrupt fixes
2011-11-13 00:32:08 -08:00
Rimas Avizienis
f86d5b1334
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
2011-11-10 11:26:13 -08:00
Rimas Avizienis
4bd0263a4a
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 03:38:59 -08:00
Rimas Avizienis
603ede8bfe
access faults now write badvaddr PCR register with faulting address
2011-11-10 02:46:09 -08:00
Rimas Avizienis
36aa4bcc9d
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 02:26:26 -08:00
Rimas Avizienis
62407b4668
more tlb/ptw fixes
2011-11-10 00:23:29 -08:00
Rimas Avizienis
6664af3bc0
cleanup before adding dtlb
2011-11-09 23:27:29 -08:00
Rimas Avizienis
9aca403aa8
more itlb integration & cleanup
2011-11-09 23:18:14 -08:00
Rimas Avizienis
c29d2821b4
cleanup, fixes, initial commit for dtlb.scala
2011-11-09 21:54:11 -08:00
Rimas Avizienis
e96430d862
integrating ITLB & PTW
2011-11-09 14:52:17 -08:00
Rimas Avizienis
7130edac8d
fix for flushed div/mul instructions
2011-11-07 01:03:47 -08:00
Rimas Avizienis
4d64099103
cleanup
2011-11-04 20:52:21 -07:00
Rimas Avizienis
4459935554
dcache fixes - all tests and ubmarks pass, hello world still broken
2011-11-04 15:40:41 -07:00
Rimas Avizienis
3a02028a35
fixes to exception and dcache miss/blocked handling
2011-11-02 13:32:32 -07:00
Rimas Avizienis
7a528d6255
fixes for div/mul hazard checking + cleanup
2011-11-01 23:14:34 -07:00
Rimas Avizienis
d8ffecf565
dcache fix
2011-11-01 22:10:06 -07:00
Rimas Avizienis
7479e085ec
dcache loads working - 1/2 cycle load/use delay depending on load type
2011-11-01 22:04:45 -07:00
Rimas Avizienis
3b3d988fde
dcache loads working - 1/2 cycle load/use delay depending on load type
2011-11-01 21:25:52 -07:00
Rimas Avizienis
2b67eee683
pipeline changes for replay on dcache miss
2011-11-01 19:05:27 -07:00
Rimas Avizienis
08b89e7710
interface cleanup, major pipeline changes
2011-11-01 17:59:27 -07:00
Rimas Avizienis
c06e2d16e4
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-25 23:02:47 -07:00