remove pc+4 piperegs and add new ex pc+4 adder
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parent
01a156eb98
commit
99a959e6b1
@ -70,12 +70,10 @@ class rocketDpath extends Component
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val id_reg_valid = Reg(resetVal = Bool(false));
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val id_reg_inst = Reg(resetVal = NOP);
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val id_reg_pc = Reg() { UFix(width = VADDR_BITS+1) };
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val id_reg_pc_plus4 = Reg() { UFix(width = VADDR_BITS+1) };
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// execute definitions
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val ex_reg_valid = Reg(resetVal = Bool(false));
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val ex_reg_pc = Reg() { UFix() };
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val ex_reg_pc_plus4 = Reg() { UFix() };
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val ex_reg_inst = Reg() { Bits() };
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val ex_reg_raddr2 = Reg() { UFix() };
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val ex_reg_rs2 = Reg() { Bits() };
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@ -127,6 +125,7 @@ class rocketDpath extends Component
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// instruction fetch stage
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val if_pc_plus4 = if_reg_pc + UFix(4);
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val ex_pc_plus4 = ex_reg_pc + UFix(4);
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val ex_sign_extend =
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Cat(Fill(52, ex_reg_inst(21)), ex_reg_inst(21,10));
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val ex_sign_extend_split =
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@ -145,7 +144,7 @@ class rocketDpath extends Component
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val if_next_pc =
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Mux(io.ctrl.sel_pc === PC_BTB, Cat(if_btb_target(VADDR_BITS-1), if_btb_target),
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Mux(io.ctrl.sel_pc === PC_EX4, ex_reg_pc_plus4,
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Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
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Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
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Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target_extended,
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Mux(io.ctrl.sel_pc === PC_PCR, wb_reg_wdata(VADDR_BITS,0), // only used for ERET
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@ -167,13 +166,12 @@ class rocketDpath extends Component
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btb.io.hit <> io.ctrl.btb_hit;
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btb.io.wen <> io.ctrl.wen_btb;
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btb.io.clr <> io.ctrl.clr_btb;
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btb.io.correct_pc4 := ex_reg_pc_plus4;
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btb.io.correct_pc4 := ex_pc_plus4;
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io.ctrl.btb_match := id_reg_pc === jr_br_target;
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// instruction decode stage
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when (!io.ctrl.stalld) {
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id_reg_pc <== if_reg_pc;
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id_reg_pc_plus4 <== if_pc_plus4;
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when(io.ctrl.killf) {
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id_reg_inst <== NOP;
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id_reg_valid <== Bool(false);
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@ -231,7 +229,6 @@ class rocketDpath extends Component
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// execute stage
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ex_reg_pc <== id_reg_pc;
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ex_reg_pc_plus4 <== id_reg_pc_plus4;
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ex_reg_inst <== id_reg_inst;
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ex_reg_raddr2 <== id_raddr2;
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ex_reg_rs2 <== id_rs2;
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@ -351,7 +348,7 @@ class rocketDpath extends Component
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// writeback select mux
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ex_wdata :=
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Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1,
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Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_reg_pc_plus4(VADDR_BITS-1)), ex_reg_pc_plus4),
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Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_pc_plus4(VADDR_BITS-1)), ex_pc_plus4),
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Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
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Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
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Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
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