dcache loads working - 1/2 cycle load/use delay depending on load type
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3b3d988fde
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@ -14,14 +14,15 @@ object Constants
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val BR_J = UFix(7, 4);
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val BR_JR = UFix(8, 4);
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val PC_4 = UFix(0, 3);
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val PC_BTB = UFix(1, 3);
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val PC_EX4 = UFix(2, 3);
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val PC_BR = UFix(3, 3);
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val PC_J = UFix(4, 3);
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val PC_JR = UFix(5, 3);
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val PC_PCR = UFix(6, 3);
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val PC_MEM = UFix(7, 3);
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val PC_4 = UFix(0, 4);
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val PC_BTB = UFix(1, 4);
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val PC_EX4 = UFix(2, 4);
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val PC_BR = UFix(3, 4);
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val PC_J = UFix(4, 4);
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val PC_JR = UFix(5, 4);
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val PC_PCR = UFix(6, 4);
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val PC_MEM = UFix(7, 4);
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val PC_MEM4 = UFix(8, 4);
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val KF_Y = UFix(1, 1);
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val KF_N = UFix(0, 1);
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@ -9,7 +9,7 @@ import Instructions._
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class ioCtrlDpath extends Bundle()
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{
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// outputs to datapath
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val sel_pc = UFix(3, 'output);
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val sel_pc = UFix(4, 'output);
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val wen_btb = Bool('output);
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val stallf = Bool('output);
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val stalld = Bool('output);
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@ -299,16 +299,19 @@ class rocketCtrl extends Component
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mem_reg_mem_type <== ex_reg_mem_type;
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}
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// replay on a D$ load miss : FIXME - add a miss signal to D$
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// replay PC when the D$ is blocked
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val replay_mem_pc = mem_reg_mem_val && !io.dmem.req_rdy;
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// replay PC+4 on a D$ load miss
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val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
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val replay_mem = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD) && !io.dmem.resp_val;
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val dcache_miss = Reg(replay_mem);
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val replay_mem_pc_plus4 = mem_cmd_load && !io.dmem.resp_val;
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val dcache_miss = Reg(replay_mem_pc_plus4);
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io.dpath.mem_load := mem_cmd_load;
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io.dpath.dcache_miss := dcache_miss;
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io.dpath.sel_pc :=
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Mux(replay_mem, PC_MEM,
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Mux(replay_mem_pc, PC_MEM,
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Mux(replay_mem_pc_plus4, PC_MEM4,
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Mux(io.dpath.exception || ex_reg_eret, PC_PCR,
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Mux(!ex_reg_btb_hit && br_taken, PC_BR,
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Mux(ex_reg_btb_hit && !br_taken || ex_reg_privileged, PC_EX4,
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@ -130,7 +130,8 @@ class rocketDpath extends Component
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Mux(io.ctrl.sel_pc === PC_J, ex_branch_target,
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Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix,
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Mux(io.ctrl.sel_pc === PC_PCR, ex_pcr(31,0).toUFix,
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Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc_plus4,
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Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
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Mux(io.ctrl.sel_pc === PC_MEM4, mem_reg_pc_plus4,
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UFix(0, 32)))))))));
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when (!io.host.start){
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@ -184,6 +185,7 @@ class rocketDpath extends Component
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// moved this here to avoid having to do forward declaration
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// TODO: cleanup
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// 64/32 bit load handling (in mem stage)
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val dmem_resp_pos = io.dmem.resp_tag(7,5).toUFix;
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val dmem_resp_type = io.dmem.resp_tag(10,8);
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