cleanup before adding dtlb
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9aca403aa8
commit
6664af3bc0
@ -162,6 +162,7 @@ object Constants
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val ASID_BITS = 7;
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val PERM_BITS = 6;
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val DTLB_ENTRIES = 8;
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val ITLB_ENTRIES = 8;
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val HAVE_FPU = Bool(false);
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@ -45,6 +45,7 @@ class rocketProc extends Component
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val ctrl = new rocketCtrl();
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val dpath = new rocketDpath();
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val dtlb = new rocketDTLB(ITLB_ENTRIES);
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val itlb = new rocketITLB(ITLB_ENTRIES);
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val ptw = new rocketPTW();
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val arb = new rocketDmemArbiter();
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@ -60,38 +61,38 @@ class rocketProc extends Component
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dpath.io.host ^^ io.host;
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dpath.io.debug ^^ io.debug;
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// FIXME: make this less verbose
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// connect ITLB to I$, ctrl, dpath
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itlb.io.cpu.invalidate := Bool(false);
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itlb.io.cpu.status := dpath.io.ctrl.status;
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itlb.io.cpu.req_val := ctrl.io.imem.req_val;
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ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
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itlb.io.cpu.req_val := ctrl.io.imem.req_val;
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itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
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// itlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
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itlb.io.cpu.req_addr := dpath.io.imem.req_addr;
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io.imem.req_val := itlb.io.cpu.resp_val;
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io.imem.req_addr := itlb.io.cpu.resp_addr;
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ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
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ctrl.io.imem.resp_val := io.imem.resp_val;
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ctrl.io.itlb_xcpt := itlb.io.cpu.exception;
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// connect page table walker to TLBs, page table base register (from PCR)
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// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
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ptw.io.itlb <> itlb.io.ptw;
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ptw.io.ptbr := dpath.io.ptbr;
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arb.io.ptw <> ptw.io.dmem;
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arb.io.mem ^^ io.dmem
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// FIXME: make this less verbose
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// connect arbiter to ctrl+dpath
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arb.io.cpu.req_val := ctrl.io.dmem.req_val;
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arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
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arb.io.cpu.req_type := ctrl.io.dmem.req_type;
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arb.io.cpu.req_addr := dpath.io.dmem.req_addr;
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arb.io.cpu.req_data := dpath.io.dmem.req_data;
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arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
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ctrl.io.dmem.req_rdy := arb.io.cpu.req_rdy;
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ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
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ctrl.io.dmem.resp_val := arb.io.cpu.resp_val;
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dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
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dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
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dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
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@ -17,7 +17,6 @@ class ioDpathAll extends Bundle()
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val ctrl = new ioCtrlDpath().flip();
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val debug = new ioDebug();
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val dmem = new ioDmem(List("req_addr", "req_data", "req_tag", "resp_val", "resp_tag", "resp_data")).flip();
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// val imem = new ioImem(List("req_addr", "resp_data")).flip();
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val imem = new ioDpathImem();
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val ptbr = UFix(PADDR_BITS, 'output);
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}
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@ -127,6 +126,7 @@ class rocketDpath extends Component
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val ex_sign_extend_split =
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Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
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// FIXME: which bits to extract should be calculated based on VADDR_BITS
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val branch_adder_rhs =
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Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(41,0), UFix(0, 1)),
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Cat(Fill(17, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0, 1)));
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@ -153,7 +153,6 @@ class rocketDpath extends Component
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when (!io.ctrl.stallf) {
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if_reg_pc <== if_next_pc;
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}
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io.imem.req_addr :=
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Mux(io.ctrl.stallf, if_reg_pc,
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@ -199,8 +198,7 @@ class rocketDpath extends Component
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UFix(0, 5)))));
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// moved this here to avoid having to do forward declaration
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// TODO: cleanup
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// FIXME: cleanup
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// 64/32 bit load handling (in mem stage)
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val dmem_resp_pos = io.dmem.resp_tag(7,5).toUFix;
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val dmem_resp_type = io.dmem.resp_tag(10,8);
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@ -358,11 +356,6 @@ class rocketDpath extends Component
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pcr.io.host.from_wen ^^ io.host.from_wen;
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pcr.io.host.from ^^ io.host.from;
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pcr.io.host.to ^^ io.host.to;
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// pcr.io.eret := ex_reg_ctrl_eret;
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// pcr.io.exception := ex_reg_ctrl_exception;
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// pcr.io.cause := ex_reg_ctrl_cause;
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// pcr.io.pc := ex_reg_pc;
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io.ctrl.status := pcr.io.status;
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io.ptbr := pcr.io.ptbr;
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