added misaligned instruction check, cleaned up badvaddr handling
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603ede8bfe
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4bd0263a4a
@ -168,7 +168,8 @@ object Constants
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// physical memory size (# 4K pages - for proxy kernel at least)
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// if you change this value, make sure to also change MEMORY_SIZE variable in memif.h
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val MEMSIZE = Bits("h2000", 64); // 32 megs
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val MEMSIZE_PAGES = 8192; // 32 megs
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val MEMSIZE = MEMSIZE_PAGES*4096;
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val HAVE_FPU = Bool(false);
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val HAVE_VEC = Bool(false);
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@ -39,9 +39,9 @@ class ioCtrlDpath extends Bundle()
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// exception handling
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val exception = Bool('output);
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val cause = UFix(5,'output);
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val badvaddr_wen = Bool('output); // high for any access fault
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val badvaddr_sel = Bool('output); // select between instruction PC or load/store addr
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val badvaddr_wen = Bool('output); // high for a load/store access fault
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// inputs from datapath
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val xcpt_ma_inst = Bool('input); // high on a misaligned/illegal virtual PC
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val btb_hit = Bool('input);
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val inst = Bits(32, 'input);
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val br_eq = Bool('input);
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@ -76,7 +76,7 @@ class ioCtrlAll extends Bundle()
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class rocketCtrl extends Component
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{
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val io = new ioCtrlAll();
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val xpr64 = Y;
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val cs =
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ListLookup(io.dpath.inst,
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@ -191,6 +191,11 @@ class rocketCtrl extends Component
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*/
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));
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val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst);
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// FIXME
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io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
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val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_sel_alu1 :: id_fn_dw :: id_fn_alu :: csremainder = cs;
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val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: id_ren_pcr :: id_wen_pcr :: id_sync :: id_eret :: id_syscall :: id_privileged :: Nil = csremainder;
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@ -227,8 +232,9 @@ class rocketCtrl extends Component
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val id_stall_waddr = sboard.io.stallc;
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val id_stall_ra = sboard.io.stallra;
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val id_reg_btb_hit = Reg(resetVal = Bool(false));
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val id_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val id_reg_btb_hit = Reg(resetVal = Bool(false));
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val id_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val id_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
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val ex_reg_br_type = Reg(){UFix(width = 4)};
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val ex_reg_btb_hit = Reg(){Bool()};
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@ -239,12 +245,14 @@ class rocketCtrl extends Component
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val ex_reg_eret = Reg(resetVal = Bool(false));
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val ex_reg_privileged = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_illegal = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_privileged = Reg(resetVal = Bool(false));
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// val ex_reg_xcpt_fpu = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_syscall = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_illegal = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_privileged = Reg(resetVal = Bool(false));
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@ -254,10 +262,12 @@ class rocketCtrl extends Component
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when (!io.dpath.stalld) {
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when (io.dpath.killf) {
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id_reg_xcpt_ma_inst <== Bool(false);
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id_reg_xcpt_itlb <== Bool(false);
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id_reg_btb_hit <== Bool(false);
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}
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otherwise{
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id_reg_xcpt_ma_inst <== if_reg_xcpt_ma_inst;
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id_reg_xcpt_itlb <== io.xcpt_itlb;
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id_reg_btb_hit <== io.dpath.btb_hit;
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}
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@ -272,7 +282,8 @@ class rocketCtrl extends Component
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ex_reg_mem_type <== UFix(0, 3);
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ex_reg_eret <== Bool(false);
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ex_reg_privileged <== Bool(false);
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ex_reg_xcpt_ma_inst <== Bool(false);
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ex_reg_xcpt_itlb <== Bool(false);
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ex_reg_xcpt_illegal <== Bool(false);
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ex_reg_xcpt_privileged <== Bool(false);
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@ -289,6 +300,7 @@ class rocketCtrl extends Component
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ex_reg_eret <== id_eret.toBool;
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ex_reg_privileged <== id_privileged.toBool;
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ex_reg_xcpt_ma_inst <== id_reg_xcpt_ma_inst;
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ex_reg_xcpt_itlb <== id_reg_xcpt_itlb;
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ex_reg_xcpt_illegal <== ~id_int_val.toBool;
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ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(5)).toBool;
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@ -314,9 +326,6 @@ class rocketCtrl extends Component
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val jr_taken = (ex_reg_br_type === BR_JR);
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val j_taken = (ex_reg_br_type === BR_J);
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io.imem.req_val := io.host.start; // FIXME
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// io.imem.req_val := Bool(true);
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io.dmem.req_val := ex_reg_mem_val && ~io.dpath.killx;
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io.dmem.req_cmd := ex_reg_mem_cmd;
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io.dmem.req_type := ex_reg_mem_type;
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@ -336,6 +345,7 @@ class rocketCtrl extends Component
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mem_reg_mem_type <== UFix(0, 3);
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mem_reg_privileged <== Bool(false);
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mem_reg_xcpt_ma_inst <== Bool(false);
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mem_reg_xcpt_itlb <== Bool(false);
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mem_reg_xcpt_illegal <== Bool(false);
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mem_reg_xcpt_privileged <== Bool(false);
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@ -350,6 +360,7 @@ class rocketCtrl extends Component
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mem_reg_mem_type <== ex_reg_mem_type;
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mem_reg_privileged <== ex_reg_privileged;
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mem_reg_xcpt_ma_inst <== ex_reg_xcpt_ma_inst;
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mem_reg_xcpt_itlb <== ex_reg_xcpt_itlb;
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mem_reg_xcpt_illegal <== mem_reg_xcpt_illegal;
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mem_reg_xcpt_privileged <== ex_reg_xcpt_privileged;
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@ -372,10 +383,10 @@ class rocketCtrl extends Component
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mem_reg_xcpt_privileged ||
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mem_reg_xcpt_fpu ||
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mem_reg_xcpt_syscall ||
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mem_reg_xcpt_itlb;
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mem_reg_xcpt_itlb ||
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mem_reg_xcpt_ma_inst;
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val mem_cause =
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// instruction address misaligned
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Mux(mem_reg_xcpt_itlb, UFix(1,5), // instruction access fault
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Mux(mem_reg_xcpt_illegal, UFix(2,5), // illegal instruction
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Mux(mem_reg_xcpt_privileged, UFix(3,5), // privileged instruction
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@ -387,13 +398,12 @@ class rocketCtrl extends Component
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// misaligned store
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Mux(io.xcpt_dtlb_ld, UFix(8,5), // load fault
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Mux(io.xcpt_dtlb_st, UFix(9,5), // store fault
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UFix(0,5))))))));
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UFix(0,5)))))))); // instruction address misaligned
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// write cause to PCR on an exception
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io.dpath.exception := mem_exception;
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io.dpath.cause := mem_cause;
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io.dpath.badvaddr_wen := io.xcpt_dtlb_ld || io.xcpt_dtlb_st || mem_reg_xcpt_itlb;
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io.dpath.badvaddr_sel := mem_reg_xcpt_itlb;
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io.dpath.badvaddr_wen := io.xcpt_dtlb_ld || io.xcpt_dtlb_st;
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// replay execute stage PC when the D$ is blocked, when the D$ misses, and for privileged instructions
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val replay_ex = (ex_reg_mem_val && !io.dmem.req_rdy) || io.dmem.resp_miss || mem_reg_privileged;
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@ -118,7 +118,6 @@ class rocketDpath extends Component
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val wb_reg_ctrl_exception = Reg(resetVal = Bool(false));
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val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
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val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val wb_reg_badvaddr_sel = Reg(resetVal = Bool(false));
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val wb_reg_badvaddr_wen = Reg(resetVal = Bool(false));
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val r_dmem_resp_val = Reg(resetVal = Bool(false));
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@ -156,7 +155,7 @@ class rocketDpath extends Component
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Mux(io.ctrl.sel_pc === PC_EVEC, pcr.io.evec,
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Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
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UFix(0, VADDR_BITS)))))))))));
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when (!io.host.start){
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if_reg_pc <== UFix(0, VADDR_BITS); //32'hFFFF_FFFC;
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}
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@ -164,6 +163,8 @@ class rocketDpath extends Component
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if_reg_pc <== if_next_pc;
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}
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io.ctrl.xcpt_ma_inst := if_next_pc(1,0) != Bits(0,2)
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io.imem.req_addr :=
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Mux(io.ctrl.stallf, if_reg_pc,
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if_next_pc);
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@ -417,7 +418,6 @@ class rocketDpath extends Component
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wb_reg_ctrl_cause <== io.ctrl.cause;
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wb_reg_mem_req_addr <== io.dmem.req_addr;
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wb_reg_badvaddr_wen <== io.ctrl.badvaddr_wen;
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wb_reg_badvaddr_sel <== io.ctrl.badvaddr_sel;
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when (io.ctrl.killm) {
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wb_reg_valid <== Bool(false);
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@ -458,9 +458,8 @@ class rocketDpath extends Component
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pcr.io.exception := wb_reg_ctrl_exception;
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pcr.io.cause := wb_reg_ctrl_cause;
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pcr.io.pc := wb_reg_pc;
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pcr.io.ldst_addr := wb_reg_mem_req_addr;
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pcr.io.badvaddr := wb_reg_mem_req_addr;
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pcr.io.badvaddr_wen := wb_reg_badvaddr_wen;
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pcr.io.badvaddr_sel := wb_reg_badvaddr_sel;
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// temporary debug outputs so things don't get optimized away
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io.debug.id_valid := id_reg_valid;
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@ -41,9 +41,8 @@ class ioDpathPCR extends Bundle()
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val exception = Bool('input);
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val cause = UFix(5, 'input);
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val badvaddr_wen = Bool('input);
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val badvaddr_sel = Bool('input);
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val pc = UFix(VADDR_BITS, 'input);
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val ldst_addr = UFix(VADDR_BITS, 'input);
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val badvaddr = UFix(VADDR_BITS, 'input);
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val eret = Bool('input);
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}
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@ -99,7 +98,7 @@ class rocketDpathPCR extends Component
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}
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when (io.badvaddr_wen) {
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reg_badvaddr <== Mux(io.badvaddr_sel, io.pc, io.ldst_addr);
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reg_badvaddr <== io.badvaddr;
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}
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when (io.exception && !reg_status_et) {
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@ -153,7 +152,7 @@ class rocketDpathPCR extends Component
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is (PCR_COUNT) { rdata <== Cat(Fill(w, reg_count(w-1)), reg_count); }
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is (PCR_COMPARE) { rdata <== Cat(Fill(w, reg_compare(w-1)), reg_compare); }
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is (PCR_CAUSE) { rdata <== Cat(Bits(0,w+27), reg_cause); }
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is (PCR_MEMSIZE) { rdata <== MEMSIZE; }
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is (PCR_MEMSIZE) { rdata <== Bits(MEMSIZE_PAGES, 64); }
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is (PCR_LOG) { rdata <== Cat(Bits(0,63), reg_log_control); }
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is (PCR_FROMHOST) { rdata <== Cat(Fill(w, reg_fromhost(w-1)), reg_fromhost); }
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is (PCR_TOHOST) { rdata <== Cat(Fill(w, reg_tohost(w-1)), reg_tohost); }
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@ -155,7 +155,8 @@ class rocketITLB(entries: Int) extends Component
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val itlb_exception =
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io.cpu.req_val && tag_hit &&
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((status_mode && !sx_array(tag_hit_addr).toBool) ||
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(!status_mode && !ux_array(tag_hit_addr).toBool));
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(!status_mode && !ux_array(tag_hit_addr).toBool) ||
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(io.cpu.resp_addr >= MEMSIZE));
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io.cpu.req_rdy := (state === s_ready);
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io.cpu.resp_val := Mux(status_vm, tag_hit, io.cpu.req_val);
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