471 lines
16 KiB
Scala
471 lines
16 KiB
Scala
package Top {
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import Chisel._
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import Node._;
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import Constants._
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import Instructions._
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import hwacha._
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class ioDpathDmem extends Bundle()
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{
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val req_addr = UFix(VADDR_BITS+1, OUTPUT);
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val req_tag = UFix(CPU_TAG_BITS, OUTPUT);
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val req_data = Bits(64, OUTPUT);
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val resp_val = Bool(INPUT);
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val resp_miss = Bool(INPUT);
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val resp_replay = Bool(INPUT);
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val resp_tag = Bits(CPU_TAG_BITS, INPUT);
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val resp_data = Bits(64, INPUT);
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val resp_data_subword = Bits(64, INPUT);
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}
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class ioDpathImem extends Bundle()
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{
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val req_addr = UFix(VADDR_BITS+1, OUTPUT);
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val resp_data = Bits(32, INPUT);
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}
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class ioDpathAll extends Bundle()
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{
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val host = new ioHost();
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val ctrl = new ioCtrlDpath().flip();
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val console = new ioConsole(List("valid","bits"));
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val debug = new ioDebug();
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val dmem = new ioDpathDmem();
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val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "resp_val", "resp_data", "resp_tag"))
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val imem = new ioDpathImem();
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val vcmdq = new io_vec_cmdq()
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val vximm1q = new io_vec_ximm1q()
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val vximm2q = new io_vec_ximm2q()
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val ptbr_wen = Bool(OUTPUT);
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val ptbr = UFix(PADDR_BITS, OUTPUT);
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val fpu = new ioDpathFPU();
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}
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class rocketDpath extends Component
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{
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val io = new ioDpathAll();
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val btb = new rocketDpathBTB(4); // # of entries in BTB
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val if_btb_target = btb.io.target;
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val pcr = new rocketDpathPCR();
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val ex_pcr = pcr.io.r.data;
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val vec = new rocketDpathVec()
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val alu = new rocketDpathALU();
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val ex_alu_out = alu.io.out;
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val ex_alu_adder_out = alu.io.adder_out;
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val div = new rocketDivider(64);
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val div_result = div.io.result;
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val div_result_tag = div.io.result_tag;
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val div_result_val = div.io.result_val;
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val mul = new rocketMultiplier();
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val mul_result = mul.io.result;
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val mul_result_tag = mul.io.result_tag;
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val mul_result_val = mul.io.result_val;
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val rfile = new rocketDpathRegfile();
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// instruction fetch definitions
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val if_reg_pc = Reg(resetVal = UFix(START_ADDR,VADDR_BITS+1));
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// instruction decode definitions
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val id_reg_valid = Reg(resetVal = Bool(false));
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val id_reg_inst = Reg(resetVal = NOP);
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val id_reg_pc = Reg() { UFix(width = VADDR_BITS+1) };
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// execute definitions
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val ex_reg_valid = Reg(resetVal = Bool(false));
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val ex_reg_pc = Reg() { UFix() };
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val ex_reg_inst = Reg() { Bits() };
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val ex_reg_raddr1 = Reg() { UFix() };
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val ex_reg_raddr2 = Reg() { UFix() };
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val ex_reg_op2 = Reg() { Bits() };
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val ex_reg_rs2 = Reg() { Bits() };
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val ex_reg_rs1 = Reg() { Bits() };
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val ex_reg_waddr = Reg() { UFix() };
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val ex_reg_ctrl_eret = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_fn_dw = Reg() { UFix() };
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val ex_reg_ctrl_fn_alu = Reg() { UFix() };
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val ex_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_mul_fn = Reg() { UFix() };
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val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_div_fn = Reg() { UFix() };
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val ex_reg_ctrl_sel_wb = Reg() { UFix() };
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val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val ex_wdata = Wire() { Bits() };
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// memory definitions
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val mem_reg_valid = Reg(resetVal = Bool(false));
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val mem_reg_pc = Reg() { UFix() };
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val mem_reg_inst = Reg() { Bits() };
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val mem_reg_rs2 = Reg() { Bits() };
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val mem_reg_waddr = Reg() { UFix() };
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val mem_reg_wdata = Reg() { Bits() };
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val mem_reg_raddr1 = Reg() { UFix() };
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val mem_reg_raddr2 = Reg() { UFix() };
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val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val mem_wdata = Wire() { Bits() };
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// writeback definitions
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val wb_reg_valid = Reg(resetVal = Bool(false));
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val wb_reg_pc = Reg() { UFix() };
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val wb_reg_inst = Reg() { Bits() };
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val wb_reg_rs2 = Reg() { Bits() };
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val wb_reg_waddr = Reg() { UFix() };
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val wb_reg_wdata = Reg() { Bits() };
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val wb_reg_raddr1 = Reg() { UFix() };
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val wb_reg_raddr2 = Reg() { UFix() };
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val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val wb_reg_ll_wb = Reg(resetVal = Bool(false));
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val wb_wdata = Wire() { Bits() };
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val dmem_resp_replay = Wire() { Bool() }
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val r_dmem_resp_replay = Reg(resetVal = Bool(false));
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val r_dmem_fp_replay = Reg(resetVal = Bool(false));
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val r_dmem_resp_waddr = Reg() { UFix() };
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// instruction fetch stage
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val if_pc_plus4 = if_reg_pc + UFix(4);
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val ex_pc_plus4 = ex_reg_pc + UFix(4);
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val ex_branch_target = ex_reg_pc + Cat(ex_reg_op2(VADDR_BITS-1,0), Bits(0,1)).toUFix
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val ex_ea_sign = Mux(ex_alu_adder_out(VADDR_BITS-1), ~ex_alu_adder_out(63,VADDR_BITS) === UFix(0), ex_alu_adder_out(63,VADDR_BITS) != UFix(0))
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val ex_effective_address = Cat(ex_ea_sign, ex_alu_adder_out(VADDR_BITS-1,0)).toUFix
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val if_next_pc =
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Mux(io.ctrl.sel_pc === PC_BTB, Cat(if_btb_target(VADDR_BITS-1), if_btb_target),
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Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
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Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
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Mux(io.ctrl.sel_pc === PC_JR, ex_effective_address,
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Mux(io.ctrl.sel_pc === PC_PCR, wb_reg_wdata(VADDR_BITS,0), // only used for ERET
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Mux(io.ctrl.sel_pc === PC_EVEC, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec),
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Mux(io.ctrl.sel_pc === PC_WB, wb_reg_pc,
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if_pc_plus4))))))); // PC_4
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when (!io.ctrl.stallf) {
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if_reg_pc := if_next_pc.toUFix;
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}
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io.ctrl.xcpt_ma_inst := if_next_pc(1,0) != Bits(0)
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io.imem.req_addr :=
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Mux(io.ctrl.stallf, if_reg_pc,
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if_next_pc.toUFix);
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btb.io.current_pc := if_reg_pc;
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btb.io.hit <> io.ctrl.btb_hit;
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btb.io.wen <> io.ctrl.wen_btb;
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btb.io.clr <> io.ctrl.clr_btb;
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btb.io.correct_pc := ex_reg_pc;
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btb.io.correct_target := ex_branch_target
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btb.io.invalidate := io.ctrl.flush_inst
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// instruction decode stage
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when (!io.ctrl.stalld) {
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id_reg_pc := if_reg_pc;
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when(io.ctrl.killf) {
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id_reg_inst := NOP;
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id_reg_valid := Bool(false);
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}
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.otherwise {
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id_reg_inst := io.imem.resp_data;
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id_reg_valid := Bool(true);
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}
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}
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val id_raddr1 = id_reg_inst(26,22).toUFix;
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val id_raddr2 = id_reg_inst(21,17).toUFix;
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// regfile read
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rfile.io.r0.en <> io.ctrl.ren2;
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rfile.io.r0.addr := id_raddr2;
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val id_rdata2 = rfile.io.r0.data;
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rfile.io.r1.en <> io.ctrl.ren1;
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rfile.io.r1.addr := id_raddr1;
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val id_rdata1 = rfile.io.r1.data;
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// destination register selection
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val id_waddr =
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Mux(io.ctrl.sel_wa === WA_RD, id_reg_inst(31,27).toUFix,
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RA); // WA_RA
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// bypass muxes
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val id_rs1 =
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Mux(io.ext_mem.req_val, Cat(io.ext_mem.req_ppn, io.ext_mem.req_idx),
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Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, ex_wdata,
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Mux(io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr, mem_wdata,
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Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
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id_rdata1))))
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val id_rs2 =
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Mux(io.ext_mem.req_val, io.ext_mem.req_data,
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Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, ex_wdata,
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Mux(io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr, mem_wdata,
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Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
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id_rdata2))))
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// immediate generation
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val id_imm_bj = io.ctrl.sel_alu2 === A2_BTYPE || io.ctrl.sel_alu2 === A2_JTYPE
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val id_imm_l = io.ctrl.sel_alu2 === A2_LTYPE
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val id_imm_zero = io.ctrl.sel_alu2 === A2_ZERO || io.ctrl.sel_alu2 === A2_RTYPE
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val id_imm_ibz = io.ctrl.sel_alu2 === A2_ITYPE || io.ctrl.sel_alu2 === A2_BTYPE || id_imm_zero
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val id_imm_sign = Mux(id_imm_bj, id_reg_inst(31),
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Mux(id_imm_l, id_reg_inst(26),
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Mux(id_imm_zero, Bits(0,1),
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id_reg_inst(21)))) // IMM_ITYPE
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val id_imm_small = Mux(id_imm_zero, Bits(0,12),
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Cat(Mux(id_imm_bj, id_reg_inst(31,27), id_reg_inst(21,17)), id_reg_inst(16,10)))
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val id_imm = Cat(Fill(32, id_imm_sign),
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Mux(id_imm_l, Cat(id_reg_inst(26,7), Bits(0,12)),
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Mux(id_imm_ibz, Cat(Fill(20, id_imm_sign), id_imm_small),
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Cat(Fill(7, id_imm_sign), id_reg_inst(31,7))))) // A2_JTYPE
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val id_op2 = Mux(io.ctrl.sel_alu2 === A2_RTYPE, id_rs2, id_imm)
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io.ctrl.inst := id_reg_inst;
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// execute stage
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ex_reg_pc := id_reg_pc;
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ex_reg_inst := id_reg_inst
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ex_reg_raddr1 := id_raddr1
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ex_reg_raddr2 := id_raddr2;
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ex_reg_op2 := id_op2;
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ex_reg_rs2 := id_rs2;
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ex_reg_rs1 := id_rs1;
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ex_reg_waddr := id_waddr;
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ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUFix;
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ex_reg_ctrl_fn_alu := io.ctrl.fn_alu;
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ex_reg_ctrl_mul_fn := io.ctrl.mul_fn;
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ex_reg_ctrl_div_fn := io.ctrl.div_fn;
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ex_reg_ctrl_sel_wb := io.ctrl.sel_wb;
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ex_reg_ctrl_ren_pcr := io.ctrl.ren_pcr;
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when(io.ctrl.killd) {
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ex_reg_valid := Bool(false);
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ex_reg_ctrl_div_val := Bool(false);
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ex_reg_ctrl_mul_val := Bool(false);
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ex_reg_ctrl_wen_pcr := Bool(false);
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ex_reg_ctrl_eret := Bool(false);
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}
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.otherwise {
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ex_reg_valid := id_reg_valid;
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ex_reg_ctrl_div_val := io.ctrl.div_val;
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ex_reg_ctrl_mul_val := io.ctrl.mul_val;
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ex_reg_ctrl_wen_pcr := io.ctrl.wen_pcr;
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ex_reg_ctrl_eret := io.ctrl.id_eret;
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}
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alu.io.dw := ex_reg_ctrl_fn_dw;
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alu.io.fn := ex_reg_ctrl_fn_alu;
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alu.io.in2 := ex_reg_op2.toUFix;
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alu.io.in1 := ex_reg_rs1.toUFix;
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// divider
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div.io.dw := ex_reg_ctrl_fn_dw;
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div.io.div_fn := ex_reg_ctrl_div_fn;
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div.io.div_val := ex_reg_ctrl_div_val;
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div.io.div_kill := io.ctrl.killm;
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div.io.div_tag := ex_reg_waddr;
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div.io.in0 := ex_reg_rs1;
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div.io.in1 := ex_reg_rs2;
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div.io.result_rdy:= !dmem_resp_replay
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io.ctrl.div_rdy := div.io.div_rdy;
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io.ctrl.div_result_val := div.io.result_val;
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// multiplier
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mul.io.mul_val := ex_reg_ctrl_mul_val;
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mul.io.mul_kill:= io.ctrl.killm;
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mul.io.dw := ex_reg_ctrl_fn_dw;
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mul.io.mul_fn := ex_reg_ctrl_mul_fn;
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mul.io.mul_tag := ex_reg_waddr;
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mul.io.in0 := ex_reg_rs1;
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mul.io.in1 := ex_reg_rs2;
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io.ctrl.mul_rdy := mul.io.mul_rdy
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io.ctrl.mul_result_val := mul.io.result_val;
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mul.io.result_rdy := !dmem_resp_replay && !div.io.result_val
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io.ctrl.ex_waddr := ex_reg_waddr; // for load/use hazard detection & bypass control
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// D$ request interface (registered inside D$ module)
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// other signals (req_val, req_rdy) connect to control module
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io.dmem.req_addr := ex_effective_address.toUFix;
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io.dmem.req_data := (if (HAVE_FPU) Mux(io.ctrl.ex_fp_val, io.fpu.store_data, mem_reg_rs2) else mem_reg_rs2)
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io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val, io.ctrl.ex_ext_mem_val).toUFix
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// processor control regfile read
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pcr.io.r.en := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_eret;
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pcr.io.r.addr :=
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Mux(ex_reg_ctrl_eret, PCR_EPC,
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ex_reg_raddr2);
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pcr.io.host.from_wen <> io.host.from_wen;
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pcr.io.host.from <> io.host.from;
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pcr.io.host.to <> io.host.to;
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io.ctrl.irq_timer := pcr.io.irq_timer;
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io.ctrl.irq_ipi := pcr.io.irq_ipi;
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io.ctrl.status := pcr.io.status;
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io.ptbr := pcr.io.ptbr;
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io.ptbr_wen := pcr.io.ptbr_wen;
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io.debug.error_mode := pcr.io.debug.error_mode;
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// branch resolution logic
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io.ctrl.br_eq := (ex_reg_rs1 === ex_reg_rs2);
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io.ctrl.br_ltu := (ex_reg_rs1.toUFix < ex_reg_rs2.toUFix);
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io.ctrl.br_lt :=
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(~(ex_reg_rs1(63) ^ ex_reg_rs2(63)) & io.ctrl.br_ltu |
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ex_reg_rs1(63) & ~ex_reg_rs2(63)).toBool;
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// time stamp counter
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val tsc_reg = Reg(resetVal = UFix(0,64));
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tsc_reg := tsc_reg + UFix(1);
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// instructions retired counter
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val irt_reg = Reg(resetVal = UFix(0,64));
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when (wb_reg_valid) { irt_reg := irt_reg + UFix(1); }
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// writeback select mux
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ex_wdata :=
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Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_pc_plus4(VADDR_BITS-1)), ex_pc_plus4),
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Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
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Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
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Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
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ex_alu_out)))).toBits; // WB_ALU
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// subword store data generation
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val storegen = new StoreDataGen
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storegen.io.typ := io.ctrl.ex_mem_type
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storegen.io.din := ex_reg_rs2
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// memory stage
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mem_reg_pc := ex_reg_pc;
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mem_reg_inst := ex_reg_inst
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mem_reg_rs2 := storegen.io.dout
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mem_reg_waddr := ex_reg_waddr;
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mem_reg_wdata := ex_wdata;
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mem_reg_raddr1 := ex_reg_raddr1
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mem_reg_raddr2 := ex_reg_raddr2;
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when (io.ctrl.killx) {
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mem_reg_valid := Bool(false);
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mem_reg_ctrl_wen_pcr := Bool(false);
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}
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.otherwise {
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mem_reg_valid := ex_reg_valid;
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mem_reg_ctrl_wen_pcr := ex_reg_ctrl_wen_pcr;
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}
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// for load/use hazard detection (load byte/halfword)
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io.ctrl.mem_waddr := mem_reg_waddr;
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io.ctrl.mem_valid := mem_reg_valid;
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mem_wdata := Mux(io.ctrl.mem_load, io.dmem.resp_data, mem_reg_wdata)
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// 32/64 bit load handling (moved to earlier in file)
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// writeback stage
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val dmem_resp_ext = io.dmem.resp_tag(0).toBool
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val dmem_resp_xpu = !io.dmem.resp_tag(0).toBool && !io.dmem.resp_tag(1).toBool
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val dmem_resp_fpu = !io.dmem.resp_tag(0).toBool && io.dmem.resp_tag(1).toBool
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val dmem_resp_waddr = io.dmem.resp_tag.toUFix >> UFix(2)
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val dmem_resp_ext_tag = io.dmem.resp_tag.toUFix >> UFix(1)
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dmem_resp_replay := io.dmem.resp_replay && dmem_resp_xpu;
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r_dmem_resp_replay := dmem_resp_replay
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r_dmem_resp_waddr := dmem_resp_waddr
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r_dmem_fp_replay := io.dmem.resp_replay && dmem_resp_fpu;
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val mem_ll_waddr = Mux(dmem_resp_replay, dmem_resp_waddr,
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|
Mux(div_result_val, div_result_tag,
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|
Mux(mul_result_val, mul_result_tag,
|
|
mem_reg_waddr)))
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|
val mem_ll_wdata = Mux(div_result_val, div_result,
|
|
Mux(mul_result_val, mul_result,
|
|
mem_reg_wdata))
|
|
val mem_ll_wb = dmem_resp_replay || div_result_val || mul_result_val
|
|
|
|
wb_reg_pc := mem_reg_pc;
|
|
wb_reg_inst := mem_reg_inst
|
|
wb_reg_ll_wb := mem_ll_wb
|
|
wb_reg_rs2 := mem_reg_rs2
|
|
wb_reg_waddr := mem_ll_waddr
|
|
wb_reg_wdata := mem_ll_wdata
|
|
wb_reg_raddr1 := mem_reg_raddr1
|
|
wb_reg_raddr2 := mem_reg_raddr2;
|
|
|
|
when (io.ctrl.killm) {
|
|
wb_reg_valid := Bool(false);
|
|
wb_reg_ctrl_wen_pcr := Bool(false);
|
|
}
|
|
.otherwise {
|
|
wb_reg_valid := mem_reg_valid;
|
|
wb_reg_ctrl_wen_pcr := mem_reg_ctrl_wen_pcr;
|
|
}
|
|
|
|
// vector datapath
|
|
vec.io.valid := wb_reg_valid
|
|
vec.io.sr_ev := pcr.io.status(SR_EV)
|
|
vec.io.inst := wb_reg_inst
|
|
vec.io.waddr := wb_reg_waddr
|
|
vec.io.raddr1 := wb_reg_raddr1
|
|
vec.io.vecbank := pcr.io.vecbank
|
|
vec.io.vecbankcnt := pcr.io.vecbankcnt
|
|
vec.io.wdata := wb_reg_wdata
|
|
vec.io.rs2 := wb_reg_rs2
|
|
|
|
// regfile write
|
|
val wb_src_dmem = Reg(io.ctrl.mem_load) && wb_reg_valid || r_dmem_resp_replay
|
|
wb_wdata :=
|
|
Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl),
|
|
Mux(wb_src_dmem, io.dmem.resp_data_subword,
|
|
wb_reg_wdata))
|
|
|
|
rfile.io.w0.addr := wb_reg_waddr
|
|
rfile.io.w0.en := io.ctrl.wb_wen || wb_reg_ll_wb
|
|
rfile.io.w0.data := wb_wdata
|
|
|
|
io.ext_mem.resp_val := Reg(io.dmem.resp_val && dmem_resp_ext, resetVal = Bool(false))
|
|
io.ext_mem.resp_tag := Reg(dmem_resp_ext_tag)
|
|
io.ext_mem.resp_data := io.dmem.resp_data_subword
|
|
|
|
io.ctrl.wb_waddr := wb_reg_waddr;
|
|
io.ctrl.mem_wb := dmem_resp_replay;
|
|
|
|
vec.io.vcmdq <> io.vcmdq
|
|
vec.io.vximm1q <> io.vximm1q
|
|
vec.io.vximm2q <> io.vximm2q
|
|
|
|
// scoreboard clear (for div/mul and D$ load miss writebacks)
|
|
io.ctrl.sboard_clr := mem_ll_wb
|
|
io.ctrl.sboard_clra := mem_ll_waddr
|
|
io.ctrl.fp_sboard_clr := r_dmem_fp_replay
|
|
io.ctrl.fp_sboard_clra := r_dmem_resp_waddr
|
|
|
|
// processor control regfile write
|
|
pcr.io.w.addr := wb_reg_raddr2;
|
|
pcr.io.w.en := wb_reg_ctrl_wen_pcr;
|
|
pcr.io.w.data := wb_reg_wdata;
|
|
|
|
pcr.io.di := io.ctrl.irq_disable;
|
|
pcr.io.ei := io.ctrl.irq_enable;
|
|
pcr.io.eret := io.ctrl.wb_eret;
|
|
pcr.io.exception := io.ctrl.exception;
|
|
pcr.io.cause := io.ctrl.cause;
|
|
pcr.io.pc := wb_reg_pc;
|
|
pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen;
|
|
io.console.bits := pcr.io.console_data;
|
|
io.console.valid := pcr.io.console_val;
|
|
}
|
|
|
|
}
|