riscv/rocket-chip
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dcache fix

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This commit is contained in:
Rimas Avizienis 2011-11-01 22:10:06 -07:00
parent 7479e085ec
commit d8ffecf565
2 changed files with 5 additions and 3 deletions
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6
rocket/src/main/scala/ctrl.scala
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@ -305,6 +305,7 @@ class rocketCtrl extends Component
val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
val replay_mem_pc_plus4 = mem_cmd_load && !io.dmem.resp_val;
val dcache_miss = Reg(replay_mem_pc_plus4);
val replay_mem = replay_mem_pc | replay_mem_pc_plus4;
io.dpath.mem_load := mem_cmd_load;
io.dpath.dcache_miss := dcache_miss;
@ -318,7 +319,7 @@ class rocketCtrl extends Component
Mux(jr_taken, PC_JR,
Mux(j_taken, PC_J,
Mux(io.dpath.btb_hit, PC_BTB,
PC_4)))))));
PC_4))))))));
io.dpath.wen_btb := ~ex_reg_btb_hit & br_taken;
@ -330,7 +331,8 @@ class rocketCtrl extends Component
io.dpath.exception |
ex_reg_privileged |
ex_reg_eret |
replay_mem;
replay_mem_pc |
replay_mem_pc_plus4;
io.dpath.stallf :=
~take_pc &

2
rocket/src/main/scala/dpath.scala
View File

@ -132,7 +132,7 @@ class rocketDpath extends Component
Mux(io.ctrl.sel_pc === PC_PCR, ex_pcr(31,0).toUFix,
Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
Mux(io.ctrl.sel_pc === PC_MEM4, mem_reg_pc_plus4,
UFix(0, 32)))))))));
UFix(0, 32))))))))));
when (!io.host.start){
if_reg_pc <== UFix(0, 32); //32'hFFFF_FFFC;