cleanup
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2db9ee12bc
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4d64099103
@ -322,14 +322,12 @@ class rocketCtrl extends Component
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}
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// replay execute stage PC when the D$ is blocked
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// val replay_mem_pc = mem_reg_mem_val && (mem_reg_mem_cmd != M_FLA) && !io.dmem.req_rdy;
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val replay_ex = ex_reg_mem_val && !io.dmem.req_rdy;
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// replay memory stage PC+4 on a D$ load miss
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// replay execute stage PC on a D$ load miss
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val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
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// val replay_mem_pc_plus4 = mem_cmd_load && !io.dmem.resp_val;
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val replay_mem = io.dmem.resp_miss;
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// val kill_ex = replay_mem_pc | replay_mem_pc_plus4 | mem_reg_privileged;
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val kill_ex = replay_ex | replay_mem | mem_reg_privileged;
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val kill_mem = io.dpath.exception;
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@ -339,14 +337,13 @@ class rocketCtrl extends Component
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io.dpath.sel_pc :=
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Mux(io.dpath.exception || mem_reg_eret, PC_PCR,
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Mux(replay_mem || mem_reg_privileged, PC_MEM4,
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Mux(replay_ex, PC_EX,
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Mux(replay_ex || replay_mem || mem_reg_privileged, PC_EX,
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Mux(!ex_reg_btb_hit && br_taken, PC_BR,
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Mux(ex_reg_btb_hit && !br_taken, PC_EX4,
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Mux(jr_taken, PC_JR,
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Mux(j_taken, PC_J,
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Mux(io.dpath.btb_hit, PC_BTB,
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PC_4))))))));
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PC_4)))))));
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io.dpath.wen_btb := ~ex_reg_btb_hit & br_taken & ~kill_ex & ~kill_mem;
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@ -110,7 +110,6 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
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val r_cpu_req_addr = Reg(resetVal = Bits(0, addrbits));
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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// val r_cpu_req_data = Reg(resetVal = Bits(0,64));
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val r_cpu_req_cmd = Reg(resetVal = Bits(0,4));
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val r_cpu_req_type = Reg(resetVal = Bits(0,3));
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val r_cpu_req_tag = Reg(resetVal = Bits(0,5));
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@ -119,7 +118,6 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
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val p_store_addr = Reg(resetVal = Bits(0,64));
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val p_store_cmd = Reg(resetVal = Bits(0,4));
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val p_store_type = Reg(resetVal = Bits(0,3));
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// val p_store_wmask = Reg(resetVal = Bits(0,64));
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val p_store_valid = Reg(resetVal = Bool(false));
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val req_load = (r_cpu_req_cmd === M_XRD);
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@ -222,7 +220,6 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
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val addr_match = (r_cpu_req_addr(tagmsb, offsetlsb) === p_store_addr(tagmsb, offsetlsb));
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val ldst_conflict = r_cpu_req_val && req_load && p_store_valid && addr_match;
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// val drain_store = ((state === s_ready) && p_store_valid && (!r_cpu_req_val || !tag_match || !req_load || addr_match))
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val drain_store =
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(state === s_ready) && p_store_valid &&
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(!(io.cpu.req_val && (io.cpu.req_cmd === M_XRD)) ||
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@ -137,8 +137,7 @@ class rocketDpath extends Component
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Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix,
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Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_pcr(31,0).toUFix,
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Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
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Mux(io.ctrl.sel_pc === PC_MEM4, mem_reg_pc_plus4,
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UFix(0, 32)))))))))));
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UFix(0, 32))))))))));
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when (!io.host.start){
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if_reg_pc <== UFix(0, 32); //32'hFFFF_FFFC;
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@ -24,7 +24,8 @@ class ioIcache(view: List[String] = null) extends Bundle (view)
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val resp_val = Bool('output);
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}
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class ioICacheDM extends Bundle() {
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class ioICacheDM extends Bundle()
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{
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val cpu = new ioImem();
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val mem = new ioIcache().flip();
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}
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@ -51,14 +52,22 @@ class rocketICacheDM(lines: Int, addrbits : Int) extends Component {
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val state = Reg(resetVal = s_reset);
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val r_cpu_req_addr = Reg(Bits(0, addrbits));
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when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) { r_cpu_req_addr <== io.cpu.req_addr; }
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when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) {
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r_cpu_req_addr <== io.cpu.req_addr;
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}
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val r_cpu_req_val = Reg(Bool(false));
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when ((state === s_ready) || (state === s_resolve_miss)) { r_cpu_req_val <== io.cpu.req_val; }
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otherwise { r_cpu_req_val <== Bool(false); }
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when ((state === s_ready) || (state === s_resolve_miss)) {
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r_cpu_req_val <== io.cpu.req_val;
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}
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otherwise {
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r_cpu_req_val <== Bool(false);
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}
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val refill_count = Reg(resetVal = UFix(0,2));
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when (io.mem.resp_val) { refill_count <== refill_count + UFix(1); }
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when (io.mem.resp_val) {
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refill_count <== refill_count + UFix(1);
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}
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// tag array
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val tag_wdata = r_cpu_req_addr(tagmsb, taglsb);
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@ -72,7 +81,9 @@ class rocketICacheDM(lines: Int, addrbits : Int) extends Component {
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val vb_array = Reg(resetVal = Bits(0, lines));
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val vb_rdata = Reg(vb_array(io.cpu.req_addr(indexmsb, indexlsb)));
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when ((state === s_refill_wait) && io.mem.resp_val) { vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1)); }
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when ((state === s_refill_wait) && io.mem.resp_val) {
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vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1));
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}
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val tag_match = vb_rdata.toBool && (tag_lookup === r_cpu_req_addr(tagmsb, taglsb));
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