riscv/rocket-chip
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add dummy mul_rdy signal

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This commit is contained in:
Andrew Waterman 2011-12-17 07:30:47 -08:00
parent 96c78829b4
commit bcceb08373
3 changed files with 7 additions and 2 deletions
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2
rocket/src/main/scala/ctrl.scala
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@ -56,6 +56,7 @@ class ioCtrlDpath extends Bundle()
val br_ltu = Bool('input);
val div_rdy = Bool('input);
val div_result_val = Bool('input);
val mul_rdy = Bool('input);
val mul_result_val = Bool('input);
val ex_waddr = UFix(5,'input); // write addr from execute stage
val mem_waddr = UFix(5,'input); // write addr from memory stage
@ -628,6 +629,7 @@ class rocketCtrl extends Component
((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
id_console_out_val && !io.console.rdy ||
id_div_val.toBool && !io.dpath.div_rdy ||
id_mul_val.toBool && !io.dpath.mul_rdy ||
io.dpath.div_result_val ||
io.dpath.mul_result_val
);

3
rocket/src/main/scala/dpath.scala
View File

@ -288,7 +288,8 @@ class rocketDpath extends Component
mul.io.mul_tag := ex_reg_waddr;
mul.io.in0 := ex_reg_rs1;
mul.io.in1 := ex_reg_rs2;
io.ctrl.mul_rdy := mul.io.mul_rdy
io.ctrl.mul_result_val := mul.io.result_val;
io.ctrl.ex_waddr := ex_reg_waddr; // for load/use hazard detection & bypass control

4
rocket/src/main/scala/multiplier.scala
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@ -7,6 +7,7 @@ import Constants._;
class ioMultiplier(width: Int) extends Bundle {
// requests
val mul_val = Bool('input);
val mul_rdy = Bool('output);
val dw = UFix(1, 'input);
val mul_fn = UFix(2, 'input);
val mul_tag = UFix(5, 'input);
@ -60,7 +61,8 @@ class rocketMultiplier extends Component {
val r_result = Reg(Reg(Reg(mul_output)));
val r_result_tag = Reg(Reg(Reg(r_tag)));
val r_result_val = Reg(Reg(Reg(r_val)));
io.mul_rdy := Bool(true)
io.result := r_result;
io.result_tag := r_result_tag;
io.result_val := r_result_val;