fix multiplier for rv32
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a8d0cd95e6
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@ -44,13 +44,11 @@ object Constants
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val A1_RS1 = UFix(0, 1);
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val A1_LUI = UFix(1, 1);
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val MUL_X = UFix(0, 3);
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val MUL_NO = UFix(0, 3);
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val MUL_64 = UFix(1, 3);
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val MUL_64H = UFix(2, 3);
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val MUL_64HU = UFix(3, 3);
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val MUL_64HSU = UFix(4, 3);
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val MUL_32 = UFix(5, 3);
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val MUL_X = UFix(0, 2);
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val MUL_LO = UFix(0, 2);
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val MUL_HU = UFix(1, 2);
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val MUL_HS = UFix(2, 2);
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val MUL_HSU = UFix(3, 2);
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val DIV_X = UFix(0, 4);
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val DIV_NO = UFix(0, 4);
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@ -24,7 +24,7 @@ class ioCtrlDpath extends Bundle()
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val fn_dw = Bool('output);
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val fn_alu = UFix(4, 'output);
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val mul_val = Bool('output);
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val mul_fn = UFix(3, 'output);
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val mul_fn = UFix(2, 'output);
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val mul_wb = Bool('output);
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val div_val = Bool('output);
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val div_fn = UFix(4, 'output);
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@ -234,11 +234,11 @@ class rocketCtrl extends Component
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SRLW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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SRAW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_RS2, A1_RS1,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MUL-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, Y,MUL_64, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MULH-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, Y,MUL_64H, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MULHU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, Y,MUL_64HU, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MULHSU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, Y,MUL_64HSU, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MULW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, Y,MUL_32, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MUL-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MULH-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HS, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MULHU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HU, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MULHSU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HSU, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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MULW-> List(xpr64, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_32, FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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DIV-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_64D, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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DIVU-> List(Y, BR_N, REN_Y,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_64DU, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
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@ -283,6 +283,7 @@ class rocketDpath extends Component
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// multiplier
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mul.io.mul_val := ex_reg_ctrl_mul_val && !io.ctrl.killx;
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mul.io.dw := ex_reg_ctrl_fn_dw;
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mul.io.mul_fn := ex_reg_ctrl_mul_fn;
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mul.io.mul_tag := ex_reg_waddr;
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mul.io.in0 := ex_reg_rs1;
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@ -7,7 +7,8 @@ import Constants._;
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class ioMultiplier(width: Int) extends Bundle {
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// requests
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val mul_val = Bool('input);
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val mul_fn = UFix(3, 'input);
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val dw = UFix(1, 'input);
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val mul_fn = UFix(2, 'input);
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val mul_tag = UFix(5, 'input);
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val in0 = Bits(width, 'input);
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val in1 = Bits(width, 'input);
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@ -22,30 +23,38 @@ class rocketMultiplier extends Component {
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val io = new ioMultiplier(64);
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val r_val = Reg(resetVal = Bool(false));
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val r_dw = Reg(resetVal = UFix(0,1));
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val r_fn = Reg(resetVal = UFix(0,3));
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val r_tag = Reg(resetVal = UFix(0,5));
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val r_in0 = Reg(resetVal = Bits(0,64));
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val r_in1 = Reg(resetVal = Bits(0,64));
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val r_lhs = Reg(resetVal = Bits(0,65));
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val r_rhs = Reg(resetVal = Bits(0,65));
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val lhs_msb = Mux(io.dw === DW_64, io.in0(63), io.in0(31)).toBool
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val lhs_sign = ((io.mul_fn === MUL_HS) || (io.mul_fn === MUL_HSU)) && lhs_msb
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val lhs_hi = Mux(io.dw === DW_64, io.in0(63,32), Fill(32, lhs_sign))
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val lhs = Cat(lhs_sign, lhs_hi, io.in0(31,0))
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val rhs_msb = Mux(io.dw === DW_64, io.in1(63), io.in1(31)).toBool
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val rhs_sign = (io.mul_fn === MUL_HS) && rhs_msb
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val rhs_hi = Mux(io.dw === DW_64, io.in1(63,32), Fill(32, rhs_sign))
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val rhs = Cat(rhs_sign, rhs_hi, io.in1(31,0))
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r_val <== io.mul_val;
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when (io.mul_val) {
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r_dw <== io.dw
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r_fn <== io.mul_fn;
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r_tag <== io.mul_tag;
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r_in0 <== io.in0;
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r_in1 <== io.in1;
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r_lhs <== lhs;
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r_rhs <== rhs;
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}
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val sxl64 = (r_fn === MUL_64H) || (r_fn === MUL_64HSU);
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val sxr64 = (r_fn === MUL_64H);
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val mul_result = r_lhs.toFix * r_rhs.toFix;
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val lhs = Cat(r_in0(63) & sxl64, r_in0);
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val rhs = Cat(r_in1(63) & sxr64, r_in1);
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val mul_output64 = Mux(r_fn === MUL_LO, mul_result(63,0), mul_result(127,64))
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val mul_output32 = Mux(r_fn === MUL_LO, mul_result(31,0), mul_result(63,31))
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val mul_output32_ext = Cat(Fill(32, mul_output32(31)), mul_output32)
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val mul_result = lhs.toFix * rhs.toFix;
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val mul_output = MuxCase(mul_result(63,0), Array(
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((r_fn === MUL_64H) || (r_fn === MUL_64HU) || (r_fn === MUL_64HSU)) -> mul_result(127,64),
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(r_fn === MUL_32) -> Cat(Fill(32, mul_result(31)), mul_result(31, 0))));
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val mul_output = Mux(r_dw === DW_64, mul_output64, mul_output32_ext)
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// just a hack for now, this should be a parameterized number of stages
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val r_result = Reg(Reg(Reg(mul_output)));
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