hwacha integration: now it compiles correctly!

rocket/src/main/scala/arbiter.scala

@@ -23,6 +23,7 @@ class ioMemArbiter extends Bundle() {
   val dcache = new ioDCache();
 //   val icache = new ioICache();
   val icache = new ioIPrefetcherMem().flip();
+  val vicache = new ioICache();
 }
 
 class rocketMemArbiter extends Component {
@@ -33,16 +34,23 @@ class rocketMemArbiter extends Component {
   // *****************************
 
   // Memory request is valid if either icache or dcache have a valid request
-  io.mem.req_val := (io.icache.req_val || io.dcache.req_val);
+  io.mem.req_val := (io.icache.req_val || io.vicache.req_val || io.dcache.req_val);
 
   // Set read/write bit.  ICache always reads
   io.mem.req_rw := Mux(io.dcache.req_val, io.dcache.req_rw, Bool(false));
 
   // Give priority to ICache
-  io.mem.req_addr := Mux(io.dcache.req_val, io.dcache.req_addr, io.icache.req_addr);
+  io.mem.req_addr :=
+    Mux(io.dcache.req_val, io.dcache.req_addr,
+    Mux(io.icache.req_val, io.icache.req_addr,
+        io.vicache.req_addr))
 
-  // low bit of tag=0 for I$, 1 for D$
-  io.mem.req_tag := Cat(Mux(io.dcache.req_val, io.dcache.req_tag, io.icache.req_tag), io.dcache.req_val)
+  // low bit of tag to indicate D$, I$, and VI$
+  val t_dcache :: t_icache :: t_vicache :: Nil = Enum(3){ UFix() }
+  io.mem.req_tag :=
+    Mux(io.dcache.req_val, Cat(io.dcache.req_tag, t_dcache),
+    Mux(io.icache.req_val, Cat(io.icache.req_tag, t_icache),
+        Cat(Bits(0, MEM_TAG_BITS-2), t_vicache)))
 
   // Just pass through write data (only D$ will write)
   io.mem.req_wdata := io.dcache.req_wdata;
@@ -55,18 +63,20 @@ class rocketMemArbiter extends Component {
   // This way, writebacks will never be interrupted by I$ refills.
   io.dcache.req_rdy := io.mem.req_rdy;
   io.icache.req_rdy := io.mem.req_rdy && !io.dcache.req_val;
+  io.vicache.req_rdy := io.mem.req_rdy && !io.dcache.req_val && !io.icache.req_val
 
   // Response will only be valid for D$ or I$ not both because of tag bits
-  io.icache.resp_val := io.mem.resp_val && !io.mem.resp_tag(0).toBool;
-  io.dcache.resp_val := io.mem.resp_val &&  io.mem.resp_tag(0).toBool;
+  io.dcache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_dcache)
+  io.icache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_icache)
+  io.vicache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_vicache)
 
   // Feed through data to both 
-  io.icache.resp_data := io.mem.resp_data;
   io.dcache.resp_data := io.mem.resp_data;
+  io.icache.resp_data := io.mem.resp_data;
+  io.vicache.resp_data := io.mem.resp_data
   
-  io.icache.resp_tag := io.mem.resp_tag >> UFix(1)
-  io.dcache.resp_tag := io.mem.resp_tag >> UFix(1)
-
+  io.dcache.resp_tag := io.mem.resp_tag >> UFix(2)
+  io.icache.resp_tag := io.mem.resp_tag >> UFix(2)
 }
 
 }

rocket/src/main/scala/consts.scala

@@ -177,7 +177,7 @@ object Constants
   // external memory interface
   val IMEM_TAG_BITS = 1;
   val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt;
-  val MEM_TAG_BITS = 1 + max(IMEM_TAG_BITS, DMEM_TAG_BITS);
+  val MEM_TAG_BITS = 2 + max(IMEM_TAG_BITS, DMEM_TAG_BITS);
   val MEM_DATA_BITS = 128;
   val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS;
   

rocket/src/main/scala/cpu.scala

@@ -30,6 +30,7 @@ class ioRocket extends Bundle()
   val console = new ioConsole();
   val host    = new ioHost();
   val imem    = new ioImem().flip();
+  val vimem   = new ioImem().flip();
   val dmem    = new ioDmem().flip();
 }
 
@@ -42,6 +43,7 @@ class rocketProc extends Component
 
   val dtlb  = new rocketDTLB(DTLB_ENTRIES);
   val itlb  = new rocketITLB(ITLB_ENTRIES);
+  val vitlb = new rocketITLB(ITLB_ENTRIES);
   val ptw   = new rocketPTW();
   val arb   = new rocketDmemArbiter();
 
@@ -130,8 +132,36 @@ class rocketProc extends Component
   {
     val vu = new vu()
 
+    vitlb.io.cpu.invalidate := dpath.io.ptbr_wen
+    vitlb.io.cpu.status     := dpath.io.ctrl.status
+    vitlb.io.cpu.req_val    := vu.io.imem_req.valid  
+    vitlb.io.cpu.req_asid   := Bits(0,ASID_BITS) // FIXME: connect to PCR
+    vitlb.io.cpu.req_vpn    := vu.io.imem_req.bits(VADDR_BITS,PGIDX_BITS).toUFix
+    io.vimem.req_idx        := vu.io.imem_req.bits(PGIDX_BITS-1,0)
+    io.vimem.req_ppn        := vitlb.io.cpu.resp_ppn
+    io.vimem.req_val        := vu.io.imem_req.valid
+    io.vimem.invalidate     := ctrl.io.dpath.flush_inst
+    vu.io.imem_resp.valid   := io.vimem.resp_val
+    vu.io.imem_resp.bits    := io.vimem.resp_data
+    // handle vitlb.io.cpu.exception
+    io.vimem.itlb_miss      := vitlb.io.cpu.resp_miss
+
     vu.io.vec_cmdq <> dpath.io.vcmdq
     vu.io.vec_ximm1q <> dpath.io.vximm1q
     vu.io.vec_ximm2q <> dpath.io.vximm2q
+
+    ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid
+    ctrl.io.ext_mem.req_cmd := vu.io.dmem_req.bits.cmd
+    ctrl.io.ext_mem.req_type := vu.io.dmem_req.bits.typ
+
+    dpath.io.ext_mem.req_val := vu.io.dmem_req.valid
+    dpath.io.ext_mem.req_idx := vu.io.dmem_req.bits.idx
+    dpath.io.ext_mem.req_ppn := vu.io.dmem_req.bits.ppn
+    dpath.io.ext_mem.req_data := vu.io.dmem_req.bits.data
+
+    vu.io.dmem_resp.valid := dpath.io.ext_mem.resp_val
+    vu.io.dmem_resp.bits.nack := ctrl.io.ext_mem.resp_nack
+    vu.io.dmem_resp.bits.data := dpath.io.ext_mem.resp_data
+    vu.io.dmem_resp.bits.tag := dpath.io.ext_mem.resp_tag
   }
 }

rocket/src/main/scala/dpath.scala

@@ -34,7 +34,7 @@ class ioDpathAll extends Bundle()
   val console = new ioConsole(List("valid","bits"));
   val debug = new ioDebug();
   val dmem  = new ioDpathDmem();
-  val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "resp_val", "resp_data", "resp_tag"))
+  val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "req_tag", "resp_val", "resp_data", "resp_tag"))
   val imem  = new ioDpathImem();
   val vcmdq = new io_vec_cmdq()
   val vximm1q = new io_vec_ximm1q()
@@ -101,6 +101,7 @@ class rocketDpath extends Component
   val ex_reg_ctrl_sel_wb    = Reg() { UFix() };
   val ex_reg_ctrl_ren_pcr   = Reg(resetVal = Bool(false));
   val ex_reg_ctrl_wen_pcr   = Reg(resetVal = Bool(false));
+  val ex_reg_ext_mem_tag    = Reg() { Bits() };
  	val ex_wdata						  = Wire() { Bits() }; 	
 
   // memory definitions
@@ -251,6 +252,7 @@ class rocketDpath extends Component
   ex_reg_ctrl_div_fn    := io.ctrl.div_fn;
   ex_reg_ctrl_sel_wb    := io.ctrl.sel_wb;
   ex_reg_ctrl_ren_pcr   := io.ctrl.ren_pcr;
+  ex_reg_ext_mem_tag    := io.ext_mem.req_tag
 
   when(io.ctrl.killd) {
     ex_reg_valid          := Bool(false);
@@ -306,7 +308,7 @@ class rocketDpath extends Component
   // other signals (req_val, req_rdy) connect to control module  
   io.dmem.req_addr  := ex_effective_address.toUFix;
   io.dmem.req_data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
-  io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val, io.ctrl.ex_ext_mem_val).toUFix
+  io.dmem.req_tag := Cat(Mux(io.ctrl.ex_ext_mem_val, ex_reg_ext_mem_tag(CPU_TAG_BITS-2, 0), Cat(ex_reg_waddr, io.ctrl.ex_fp_val)), io.ctrl.ex_ext_mem_val).toUFix
 
 	// processor control regfile read
   pcr.io.r.en   := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_eret;

rocket/src/main/scala/top.scala

@@ -17,12 +17,14 @@ class Top() extends Component {
   val cpu       = new rocketProc();
   val icache    = new rocketICache(128, 2); // 128 sets x 2 ways
   val icache_pf = new rocketIPrefetcher();
+  val vicache   = new rocketICache(128, 2); // 128 sets x 2 ways
   val dcache    = new HellaCache();
   val arbiter   = new rocketMemArbiter();
 
   arbiter.io.mem    <> io.mem; 
   arbiter.io.dcache <> dcache.io.mem;
   arbiter.io.icache <> icache_pf.io.mem;
+  arbiter.io.vicache <> vicache.io.mem
 
   cpu.io.host       <> io.host;
   cpu.io.debug      <> io.debug;
@@ -30,6 +32,7 @@ class Top() extends Component {
 
   icache.io.mem     <> icache_pf.io.icache;
   cpu.io.imem       <> icache.io.cpu;
+  cpu.io.vimem      <> vicache.io.cpu;
   cpu.io.dmem       <> dcache.io.cpu;
   
 }