Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Andrew Waterman
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95c5147dc5
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Add RISC-V instruction disassembler
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2013-06-13 10:31:04 -07:00 |
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Andrew Waterman
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50ccc20bf3
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replace RDNPC with AUIPC
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2013-04-22 04:20:15 -07:00 |
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Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
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Andrew Waterman
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8b439ef20d
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only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
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2013-04-04 17:07:08 -07:00 |
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Henry Cook
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6d2541aced
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-20 14:12:36 -07:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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78868f6075
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add config option to trade mul/div area for speed
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2013-01-06 03:47:17 -08:00 |
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Andrew Waterman
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05f19b21d0
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merge multiplier and divider
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2012-12-12 02:22:47 -08:00 |
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Andrew Waterman
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4608660f6e
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torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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Andrew Waterman
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9c857b83f0
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refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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Andrew Waterman
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352bb464b5
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clock gate X/M and M/W store data registers
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2012-11-26 20:33:41 -08:00 |
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Andrew Waterman
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de2f28193a
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get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
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Andrew Waterman
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c036cdc1ea
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add option for 2-cycle load-use delay
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2012-11-24 22:01:08 -08:00 |
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Andrew Waterman
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72f94d1141
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fix virtual address sign extension detection
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2012-11-20 04:06:57 -08:00 |
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Andrew Waterman
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29bc361d6c
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remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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Andrew Waterman
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5a7777fe4d
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clock gate integer datapath more aggressively
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2012-11-17 06:48:44 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Yunsup Lee
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8764fe786a
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refactored vector tlb
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2012-11-06 23:53:52 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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Andrew Waterman
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5b20ed71be
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move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
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2012-11-05 01:30:57 -08:00 |
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Andrew Waterman
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7380c9fe60
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aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
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Andrew Waterman
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5773cbb68a
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rejigger htif to use UncoreConfiguration
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2012-10-18 17:26:03 -07:00 |
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Henry Cook
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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Andrew Waterman
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197154c485
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use BTB for JALR
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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661f8e635b
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merge I$, ITLB, BTB into Frontend
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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27ddff1adb
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simplify and improve multiplier
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2012-10-16 02:24:37 -07:00 |
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Henry Cook
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8970b635b2
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improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
|
Henry Cook
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9025d0610c
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first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
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Henry Cook
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dfdfddebe8
|
constants as traits
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2012-10-07 22:20:03 -07:00 |
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Huy Vo
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0a97d6ab4d
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type casting
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2012-07-18 13:03:35 -07:00 |
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Andrew Waterman
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4e44ed7400
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allow back pressure on IPI requests
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2012-07-17 22:55:40 -07:00 |
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Huy Vo
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Huy Vo
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Henry Cook
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622a801bb1
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Refactored cpu/cache interface to use nested bundles
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2012-05-02 11:54:28 -07:00 |
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Andrew Waterman
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7f254d9670
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refine FP bugfixes
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2012-04-01 14:52:33 -07:00 |
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Huy Vo
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c7c35322c2
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two bug fixes to fpu
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2012-03-31 22:23:51 -07:00 |
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Yunsup Lee
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a70f0414fa
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fix a workaroundable bug
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2012-03-26 20:51:54 -07:00 |
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Andrew Waterman
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86d56ff67b
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refactor cpu/i$/d$ into Tile (rather than Top)
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2012-03-24 16:57:28 -07:00 |
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Andrew Waterman
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54fa6f660d
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new supervisor mode
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2012-03-24 13:03:31 -07:00 |
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Yunsup Lee
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aaed0241af
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get rid of vxcptwait
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2012-03-21 15:09:04 -07:00 |
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Andrew Waterman
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a47eeb9571
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retime D$ bypass into beginning of EX stage
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2012-03-16 18:35:54 -07:00 |
|
Yunsup Lee
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b19d783fbd
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add vector irq handler
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2012-03-14 14:15:28 -07:00 |
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Yunsup Lee
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040d62f372
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refactored vector exception handling interface
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2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
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b100544b25
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datapath to read out vector state
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2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
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a1b30282dd
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major refactoring on vector exception interface
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2012-03-09 01:09:22 -08:00 |
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Yunsup Lee
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d4ec7ff4d9
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refined vector exception interface
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2012-03-03 16:11:54 -08:00 |
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