Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
This commit is contained in:
Henry Cook
parent
e7bf07d55e
commit
8766438bb9
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@ -45,8 +45,8 @@ class rocketProc extends Component
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val arb = new rocketDmemArbiter();
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ctrl.io.dpath <> dpath.io.ctrl;
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dpath.io.host ^^ io.host;
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dpath.io.debug ^^ io.debug;
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dpath.io.host <> io.host;
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dpath.io.debug <> io.debug;
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// FIXME: try to make this more compact
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@ -86,7 +86,7 @@ class rocketProc extends Component
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ptw.io.itlb <> itlb.io.ptw;
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ptw.io.ptbr := dpath.io.ptbr;
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arb.io.ptw <> ptw.io.dmem;
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arb.io.mem ^^ io.dmem
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arb.io.mem <> io.dmem
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// connect arbiter to ctrl+dpath+DTLB
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arb.io.cpu.req_val := ctrl.io.dmem.req_val;
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@ -162,9 +162,9 @@ class rocketDCacheDM_flush(lines: Int) extends Component {
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dcache.io.cpu.req_ppn := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn);
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dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
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dcache.io.cpu.req_type := io.cpu.req_type;
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dcache.io.cpu.req_data ^^ io.cpu.req_data;
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dcache.io.cpu.req_data <> io.cpu.req_data;
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dcache.io.cpu.req_kill := io.cpu.req_kill && !flush_waiting;
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dcache.io.mem ^^ io.mem;
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dcache.io.mem <> io.mem;
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io.cpu.xcpt_ma_ld := dcache.io.cpu.xcpt_ma_ld;
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io.cpu.xcpt_ma_st := dcache.io.cpu.xcpt_ma_st;
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@ -163,9 +163,9 @@ class rocketDpath extends Component
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if_next_pc.toUFix);
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btb.io.current_pc4 := if_pc_plus4;
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btb.io.hit ^^ io.ctrl.btb_hit;
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btb.io.wen ^^ io.ctrl.wen_btb;
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btb.io.clr ^^ io.ctrl.clr_btb;
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btb.io.hit <> io.ctrl.btb_hit;
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btb.io.wen <> io.ctrl.wen_btb;
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btb.io.clr <> io.ctrl.clr_btb;
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btb.io.correct_pc4 := ex_reg_pc_plus4;
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io.ctrl.btb_match := id_reg_pc === jr_br_target;
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@ -187,11 +187,11 @@ class rocketDpath extends Component
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val id_raddr2 = id_reg_inst(21,17).toUFix;
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// regfile read
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rfile.io.r0.en ^^ io.ctrl.ren2;
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rfile.io.r0.en <> io.ctrl.ren2;
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rfile.io.r0.addr := id_raddr2;
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val id_rdata2 = rfile.io.r0.data;
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rfile.io.r1.en ^^ io.ctrl.ren1;
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rfile.io.r1.en <> io.ctrl.ren1;
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rfile.io.r1.addr := id_raddr1;
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val id_rdata1 = rfile.io.r1.data;
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@ -324,9 +324,9 @@ class rocketDpath extends Component
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Mux(ex_reg_ctrl_eret, PCR_EPC,
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ex_reg_raddr2);
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pcr.io.host.from_wen ^^ io.host.from_wen;
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pcr.io.host.from ^^ io.host.from;
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pcr.io.host.to ^^ io.host.to;
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pcr.io.host.from_wen <> io.host.from_wen;
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pcr.io.host.from <> io.host.from;
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pcr.io.host.to <> io.host.to;
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io.ctrl.irq_timer := pcr.io.irq_timer;
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io.ctrl.irq_ipi := pcr.io.irq_ipi;
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@ -341,9 +341,9 @@ class MSHRFile extends Component {
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alloc_arb.io.out.ready := io.req_val && !idx_match
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meta_req_arb.io.out ^^ io.meta_req
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mem_req_arb.io.out ^^ io.mem_req
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replay_arb.io.out ^^ io.replay
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meta_req_arb.io.out <> io.meta_req
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mem_req_arb.io.out <> io.mem_req
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replay_arb.io.out <> io.replay
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io.req_rdy := Mux(idx_match, tag_match && sec_rdy, pri_rdy)
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io.mem_resp_idx := mem_resp_idx_mux.io.out
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@ -810,6 +810,7 @@ class HellaCacheDM(lines: Int) extends Component {
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p_store_type <== r_cpu_req_type
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p_store_cmd <== r_cpu_req_cmd
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p_store_data <== storegen.io.dout
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p_store_way_id <== UFix(0)
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}
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// miss handling
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@ -93,13 +93,13 @@ class queueSimplePF[T <: Data](entries: Int)(data: => T) extends Component
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{
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override val io = new ioQueueSimplePF()(data);
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val ctrl = new queueCtrl(entries);
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ctrl.io.q_reset ^^ io.q_reset;
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ctrl.io.deq_val ^^ io.deq.valid;
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ctrl.io.enq_rdy ^^ io.enq.ready;
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ctrl.io.enq_val ^^ io.enq.valid;
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ctrl.io.deq_rdy ^^ io.deq.ready;
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ctrl.io.q_reset <> io.q_reset;
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ctrl.io.deq_val <> io.deq.valid;
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ctrl.io.enq_rdy <> io.enq.ready;
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ctrl.io.enq_val <> io.enq.valid;
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ctrl.io.deq_rdy <> io.deq.ready;
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val ram = Mem(entries, ctrl.io.wen, ctrl.io.waddr, io.enq.bits);
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ram.read(ctrl.io.raddr) ^^ io.deq.bits;
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ram.read(ctrl.io.raddr) <> io.deq.bits;
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}
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// TODO: SHOULD USE INHERITANCE BUT BREAKS INTROSPECTION CODE
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@ -191,7 +191,7 @@ class queueDpathFlow[T <: Data](entries: Int)(data: => T) extends Component
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override val io = new ioQueueDpathFlow(addr_sz)(data);
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val ram = Mem(entries, io.wen, io.waddr, io.enq_bits);
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val rout = ram(io.raddr);
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Mux(io.flowthru, io.enq_bits, rout) ^^ io.deq_bits;
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Mux(io.flowthru, io.enq_bits, rout) <> io.deq_bits;
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}
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class ioQueueFlowPF[T <: Data](data: => T) extends Bundle()
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@ -210,17 +210,17 @@ class queueFlowPF[T <: Data](entries: Int)(data: => T) extends Component
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val ctrl = new queueCtrlFlow(entries);
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val dpath = new queueDpathFlow(entries)(data);
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ctrl.io.deq_rdy ^^ io.deq_rdy;
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ctrl.io.deq_rdy <> io.deq_rdy;
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ctrl.io.wen <> dpath.io.wen;
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ctrl.io.raddr <> dpath.io.raddr;
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ctrl.io.waddr <> dpath.io.waddr;
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ctrl.io.flowthru <> dpath.io.flowthru;
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ctrl.io.enq_val ^^ io.enq_val;
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dpath.io.enq_bits ^^ io.enq_bits;
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ctrl.io.enq_val <> io.enq_val;
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dpath.io.enq_bits <> io.enq_bits;
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ctrl.io.deq_val ^^ io.deq_val;
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ctrl.io.enq_rdy ^^ io.enq_rdy;
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dpath.io.deq_bits ^^ io.deq_bits;
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ctrl.io.deq_val <> io.deq_val;
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ctrl.io.enq_rdy <> io.enq_rdy;
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dpath.io.deq_bits <> io.deq_bits;
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}
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}
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@ -20,13 +20,13 @@ class Top() extends Component {
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val dcache = new HellaCacheDM(128);
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val arbiter = new rocketMemArbiter();
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arbiter.io.mem ^^ io.mem;
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arbiter.io.mem <> io.mem;
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arbiter.io.dcache <> dcache.io.mem;
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arbiter.io.icache <> icache_pf.io.mem;
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cpu.io.host ^^ io.host;
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cpu.io.debug ^^ io.debug;
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cpu.io.console ^^ io.console;
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cpu.io.host <> io.host;
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cpu.io.debug <> io.debug;
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cpu.io.console <> io.console;
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icache.io.mem <> icache_pf.io.icache;
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cpu.io.imem <> icache.io.cpu;
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@ -102,8 +102,8 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
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for (i <- 1 to n-1)
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vout = vout || io.in(i).valid
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vout ^^ io.out.valid
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dout ^^ io.out.bits
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vout <> io.out.valid
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dout <> io.out.bits
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}
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class ioPriorityDecoder(in_width: Int, out_width: Int) extends Bundle
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