474 lines
18 KiB
Scala
474 lines
18 KiB
Scala
package Top {
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import Chisel._
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import Node._;
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import Constants._
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import Instructions._
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class ioDpathAll extends Bundle()
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{
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val host = new ioHost();
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val ctrl = new ioCtrlDpath().flip();
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val debug = new ioDebug();
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val dmem = new ioDmem(List("req_addr", "req_data", "req_tag", "resp_val", "resp_tag", "resp_data")).flip();
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val imem = new ioImem(List("req_addr", "resp_data")).flip();
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}
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class rocketDpath extends Component
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{
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val io = new ioDpathAll();
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val btb = new rocketDpathBTB();
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val if_btb_target = btb.io.target;
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val pcr = new rocketDpathPCR();
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val ex_pcr = pcr.io.r.data;
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val alu = new rocketDpathALU();
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val ex_alu_out = alu.io.out;
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val ex_jr_target = ex_alu_out(31,0);
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val div = new rocketDivider(64);
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val div_result = div.io.div_result_bits;
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val div_result_tag = div.io.div_result_tag;
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val div_result_val = div.io.div_result_val;
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val mul = new rocketMultiplier();
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val mul_result = mul.io.result;
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val mul_result_tag = mul.io.result_tag;
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val mul_result_val = mul.io.result_val;
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val rfile = new rocketDpathRegfile();
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// instruction fetch definitions
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val if_reg_pc = Reg(width = 32, resetVal = UFix(0, 32));
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// instruction decode definitions
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val id_reg_pc = Reg(resetVal = UFix(0,32));
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val id_reg_pc_plus4 = Reg(resetVal = UFix(0,32));
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val id_reg_inst = Reg(resetVal = NOP);
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// execute definitions
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val ex_reg_pc = Reg(resetVal = UFix(0,32));
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val ex_reg_pc_plus4 = Reg(resetVal = UFix(0,32));
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val ex_reg_inst = Reg(resetVal = Bits(0,32));
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val ex_reg_raddr2 = Reg(resetVal = UFix(0,5));
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val ex_reg_raddr1 = Reg(resetVal = UFix(0,5));
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val ex_reg_rs2 = Reg(resetVal = Bits(0,64));
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val ex_reg_rs1 = Reg(resetVal = Bits(0,64));
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val ex_reg_waddr = Reg(resetVal = UFix(0,5));
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val ex_reg_ctrl_sel_alu2 = Reg(resetVal = A2_X);
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val ex_reg_ctrl_sel_alu1 = Reg(resetVal = A1_X);
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val ex_reg_ctrl_fn_dw = Reg(resetVal = DW_X);
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val ex_reg_ctrl_fn_alu = Reg(resetVal = FN_X);
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val ex_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_mul_fn = Reg(resetVal = MUL_X);
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val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_div_fn = Reg(resetVal = DIV_X);
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val ex_reg_ctrl_sel_wb = Reg(resetVal = WB_X);
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val ex_reg_ctrl_wen = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_eret = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_exception = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_cause = Reg(resetVal = UFix(0,5));
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val ex_wdata = Wire() { Bits() };
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// memory definitions
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val mem_reg_pc = Reg(resetVal = UFix(0,32));
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val mem_reg_pc_plus4 = Reg(resetVal = UFix(0,32));
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val mem_reg_waddr = Reg(resetVal = UFix(0,5));
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val mem_reg_wdata = Reg(resetVal = Bits(0,64));
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val mem_reg_raddr2 = Reg(resetVal = UFix(0,5));
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val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_div_val = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_wen = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val mem_reg_ctrl_exception = Reg(resetVal = Bool(false));
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// writeback definitions
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val wb_reg_pc = Reg(resetVal = UFix(0,32));
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val wb_reg_pc_plus4 = Reg(resetVal = UFix(0,32));
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val wb_reg_waddr = Reg(resetVal = UFix(0,5));
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val wb_reg_wdata = Reg(resetVal = Bits(0,64));
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val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
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val wb_reg_raddr2 = Reg(resetVal = UFix(0,5));
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val wb_reg_ctrl_div_val = Reg(resetVal = Bool(false));
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val wb_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
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val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
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val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val r_dmem_resp_val = Reg(resetVal = Bool(false));
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val r_dmem_resp_waddr = Reg(resetVal = UFix(0,5));
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val r_dmem_resp_pos = Reg(resetVal = UFix(0,3));
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val r_dmem_resp_type = Reg(resetVal = Bits(0,3));
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val r_dmem_resp_data = Reg(resetVal = Bits(0,64));
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// instruction fetch stage
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val if_pc_plus4 = if_reg_pc + UFix(4, 32);
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val ex_sign_extend =
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Cat(Fill(52, ex_reg_inst(21)), ex_reg_inst(21,10));
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val ex_sign_extend_split =
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Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
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val branch_adder_rhs =
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Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(30,0), UFix(0, 1)),
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Cat(Fill(6, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0, 1)));
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val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;
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btb.io.correct_target := ex_branch_target;
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val if_next_pc =
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Mux(io.ctrl.sel_pc === PC_4, if_pc_plus4,
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Mux(io.ctrl.sel_pc === PC_BTB, if_btb_target,
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Mux(io.ctrl.sel_pc === PC_EX4, ex_reg_pc_plus4,
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Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
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Mux(io.ctrl.sel_pc === PC_J, ex_branch_target,
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Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix,
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Mux(io.ctrl.sel_pc === PC_PCR, ex_pcr(31,0).toUFix,
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Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
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Mux(io.ctrl.sel_pc === PC_MEM4, mem_reg_pc_plus4,
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UFix(0, 32))))))))));
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when (!io.host.start){
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if_reg_pc <== UFix(0, 32); //32'hFFFF_FFFC;
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}
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when (!io.ctrl.stallf) {
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if_reg_pc <== if_next_pc;
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}
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io.imem.req_addr :=
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Mux(io.ctrl.stallf, if_reg_pc,
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if_next_pc);
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btb.io.current_pc4 := if_pc_plus4;
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btb.io.hit ^^ io.ctrl.btb_hit;
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btb.io.wen ^^ io.ctrl.wen_btb;
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btb.io.correct_pc4 := ex_reg_pc_plus4;
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// instruction decode stage
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when (!io.ctrl.stalld) {
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id_reg_pc <== if_reg_pc;
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id_reg_pc_plus4 <== if_pc_plus4;
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when(io.ctrl.killf) {
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id_reg_inst <== NOP;
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}
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otherwise {
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id_reg_inst <== io.imem.resp_data;
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}
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}
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val id_raddr1 = id_reg_inst(26,22).toUFix;
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val id_raddr2 = id_reg_inst(21,17).toUFix;
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// regfile read
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rfile.io.r0.en ^^ io.ctrl.ren2;
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rfile.io.r0.addr := id_raddr2;
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val id_rdata2 = rfile.io.r0.data;
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rfile.io.r1.en ^^ io.ctrl.ren1;
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rfile.io.r1.addr := id_raddr1;
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val id_rdata1 = rfile.io.r1.data;
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// destination register selection
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val id_waddr =
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Mux(io.ctrl.div_wb, div_result_tag,
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Mux(io.ctrl.mul_wb, mul_result_tag,
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Mux(io.ctrl.sel_wa === WA_RD, id_reg_inst(31,27).toUFix,
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Mux(io.ctrl.sel_wa === WA_RA, RA,
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UFix(0, 5)))));
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// moved this here to avoid having to do forward declaration
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// TODO: cleanup
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// 64/32 bit load handling (in mem stage)
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val dmem_resp_pos = io.dmem.resp_tag(7,5).toUFix;
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val dmem_resp_type = io.dmem.resp_tag(10,8);
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val mem_dmem_resp_data_w =
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Mux(dmem_resp_pos(2).toBool, io.dmem.resp_data(63, 32), io.dmem.resp_data(31, 0));
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val mem_dmem_resp_data =
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Mux(dmem_resp_type === MT_D, io.dmem.resp_data,
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Mux(dmem_resp_type === MT_W, Cat(Fill(32, mem_dmem_resp_data_w(31)), mem_dmem_resp_data_w),
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Cat(UFix(0,32), mem_dmem_resp_data_w)));
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// crossbar/sign extension for 8/16 bit loads (in writeback stage)
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val dmem_resp_data_h =
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Mux(r_dmem_resp_pos(1).toBool, r_dmem_resp_data(31, 16), r_dmem_resp_data(15, 0));
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val dmem_resp_data_b =
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Mux(r_dmem_resp_pos(0).toBool, dmem_resp_data_h(15, 8), dmem_resp_data_h(7, 0));
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val dmem_resp_data_final =
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Mux(r_dmem_resp_type === MT_B, Cat(Fill(56, dmem_resp_data_b(7)), dmem_resp_data_b),
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Mux(r_dmem_resp_type === MT_BU, Cat(UFix(0, 56), dmem_resp_data_b),
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Mux(r_dmem_resp_type === MT_H, Cat(Fill(48, dmem_resp_data_h(15)), dmem_resp_data_h),
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Mux(r_dmem_resp_type === MT_HU, Cat(UFix(0, 48), dmem_resp_data_h),
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Mux((r_dmem_resp_type === MT_W) ||
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(r_dmem_resp_type === MT_WU) ||
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(r_dmem_resp_type === MT_D), r_dmem_resp_data,
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UFix(0,64))))));
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// bypass muxes
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val id_rs1 =
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Mux(io.ctrl.div_wb, div_result,
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Mux(io.ctrl.mul_wb, mul_result,
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Mux(id_raddr1 != UFix(0, 5) && ex_reg_ctrl_wen && id_raddr1 === ex_reg_waddr, ex_wdata,
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Mux(id_raddr1 != UFix(0, 5) && mem_reg_ctrl_wen && id_raddr1 === mem_reg_waddr, mem_reg_wdata,
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Mux(id_raddr1 != UFix(0, 5) && io.ctrl.mem_load && id_raddr1 === mem_reg_waddr, mem_dmem_resp_data,
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Mux(id_raddr1 != UFix(0, 5) && r_dmem_resp_val && id_raddr1 === r_dmem_resp_waddr, dmem_resp_data_final,
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Mux(id_raddr1 != UFix(0, 5) && wb_reg_ctrl_wen && id_raddr1 === wb_reg_waddr, wb_reg_wdata,
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id_rdata1)))))));
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val id_rs2 =
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Mux(id_raddr2 != UFix(0, 5) && ex_reg_ctrl_wen && id_raddr2 === ex_reg_waddr, ex_wdata,
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Mux(id_raddr2 != UFix(0, 5) && mem_reg_ctrl_wen && id_raddr2 === mem_reg_waddr, mem_reg_wdata,
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Mux(id_raddr2 != UFix(0, 5) && io.ctrl.mem_load && id_raddr2 === mem_reg_waddr, mem_dmem_resp_data,
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Mux(id_raddr2 != UFix(0, 5) && r_dmem_resp_val && id_raddr2 === r_dmem_resp_waddr, dmem_resp_data_final,
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Mux(id_raddr2 != UFix(0, 5) && wb_reg_ctrl_wen && id_raddr2 === wb_reg_waddr, wb_reg_wdata,
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id_rdata2)))));
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// write value to cause register based on exception type
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val id_exception = io.ctrl.xcpt_illegal || io.ctrl.xcpt_privileged || io.ctrl.xcpt_fpu || io.ctrl.xcpt_syscall;
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val id_cause =
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Mux(io.ctrl.xcpt_illegal, UFix(2,5),
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Mux(io.ctrl.xcpt_privileged, UFix(3,5),
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Mux(io.ctrl.xcpt_fpu, UFix(4,5),
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Mux(io.ctrl.xcpt_syscall, UFix(6,5),
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UFix(0,5)))));
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io.ctrl.inst := id_reg_inst;
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// execute stage
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ex_reg_pc <== id_reg_pc;
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ex_reg_pc_plus4 <== id_reg_pc_plus4;
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ex_reg_inst <== id_reg_inst;
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ex_reg_raddr2 <== id_raddr2;
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ex_reg_raddr1 <== id_raddr1;
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ex_reg_rs2 <== id_rs2;
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ex_reg_rs1 <== id_rs1;
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ex_reg_waddr <== id_waddr;
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ex_reg_ctrl_sel_alu2 <== io.ctrl.sel_alu2;
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ex_reg_ctrl_sel_alu1 <== io.ctrl.sel_alu1.toUFix;
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ex_reg_ctrl_fn_dw <== io.ctrl.fn_dw.toUFix;
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ex_reg_ctrl_fn_alu <== io.ctrl.fn_alu;
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ex_reg_ctrl_mul_fn <== io.ctrl.mul_fn;
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ex_reg_ctrl_div_fn <== io.ctrl.div_fn;
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ex_reg_ctrl_ll_wb <== io.ctrl.div_wb | io.ctrl.mul_wb; // TODO: verify
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ex_reg_ctrl_sel_wb <== io.ctrl.sel_wb;
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ex_reg_ctrl_ren_pcr <== io.ctrl.ren_pcr;
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ex_reg_ctrl_cause <== id_cause;
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when(io.ctrl.killd) {
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ex_reg_ctrl_div_val <== Bool(false);
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ex_reg_ctrl_mul_val <== Bool(false);
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ex_reg_ctrl_wen <== Bool(false);
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ex_reg_ctrl_wen_pcr <== Bool(false);
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ex_reg_ctrl_eret <== Bool(false);
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ex_reg_ctrl_exception <== Bool(false);
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}
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otherwise {
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ex_reg_ctrl_div_val <== io.ctrl.div_val;
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ex_reg_ctrl_mul_val <== io.ctrl.mul_val;
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ex_reg_ctrl_wen <== io.ctrl.wen;
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ex_reg_ctrl_wen_pcr <== io.ctrl.wen_pcr;
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ex_reg_ctrl_eret <== io.ctrl.eret;
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ex_reg_ctrl_exception <== id_exception;
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}
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val ex_alu_in2 =
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Mux(ex_reg_ctrl_sel_alu2 === A2_0, UFix(0, 64),
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Mux(ex_reg_ctrl_sel_alu2 === A2_SEXT, ex_sign_extend,
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Mux(ex_reg_ctrl_sel_alu2 === A2_SPLIT, ex_sign_extend_split,
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Mux(ex_reg_ctrl_sel_alu2 === A2_RS2, ex_reg_rs2,
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UFix(0, 64)))));
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val ex_alu_in1 =
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Mux(ex_reg_ctrl_sel_alu1 === A1_RS1, ex_reg_rs1,
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Mux(ex_reg_ctrl_sel_alu1 === A1_LUI, Cat(Fill(32, ex_reg_inst(26)),ex_reg_inst(26,7),UFix(0, 12)),
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UFix(0, 64)));
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val ex_alu_shamt =
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Cat(ex_alu_in2(5) & ex_reg_ctrl_fn_dw === DW_64, ex_alu_in2(4,0)).toUFix;
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alu.io.dw := ex_reg_ctrl_fn_dw;
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alu.io.fn := ex_reg_ctrl_fn_alu;
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alu.io.shamt := ex_alu_shamt.toUFix;
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alu.io.in2 := ex_alu_in2.toUFix;
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alu.io.in1 := ex_alu_in1.toUFix;
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// divider
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div.io.div_fn := ex_reg_ctrl_div_fn;
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div.io.div_val := ex_reg_ctrl_div_val;
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div.io.div_waddr := ex_reg_waddr;
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div.io.dpath_rs1 := ex_reg_rs1;
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div.io.dpath_rs2 := ex_reg_rs2;
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div.io.div_result_rdy := io.ctrl.div_wb;
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io.ctrl.div_rdy := div.io.div_rdy;
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io.ctrl.div_result_val := div.io.div_result_val;
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// multiplier
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mul.io.mul_val := ex_reg_ctrl_mul_val;
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mul.io.mul_fn := ex_reg_ctrl_mul_fn;
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mul.io.mul_tag := ex_reg_waddr;
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mul.io.in0 := ex_reg_rs1;
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mul.io.in1 := ex_reg_rs2;
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io.ctrl.mul_result_val := mul.io.result_val;
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io.ctrl.ex_waddr := ex_reg_waddr; // for load/use hazard detection
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// D$ request interface (registered inside D$ module)
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// other signals (req_val, req_rdy) connect to control module
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io.dmem.req_addr := ex_alu_out;
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io.dmem.req_data := ex_reg_rs2;
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io.dmem.req_tag := ex_reg_waddr;
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// processor control regfile read
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pcr.io.r.en := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_exception | ex_reg_ctrl_eret;
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pcr.io.r.addr :=
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Mux(ex_reg_ctrl_exception, PCR_EVEC,
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Mux(ex_reg_ctrl_eret, PCR_EPC,
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ex_reg_raddr2));
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pcr.io.host.from_wen ^^ io.host.from_wen;
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pcr.io.host.from ^^ io.host.from;
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pcr.io.host.to ^^ io.host.to;
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pcr.io.eret := ex_reg_ctrl_eret;
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pcr.io.exception := ex_reg_ctrl_exception;
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pcr.io.cause := ex_reg_ctrl_cause;
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pcr.io.pc := ex_reg_pc;
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io.ctrl.status := pcr.io.status;
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io.debug.error_mode := pcr.io.debug.error_mode;
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io.debug.log_control := pcr.io.debug.log_control;
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// branch resolution logic
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io.ctrl.br_eq := (ex_reg_rs1 === ex_reg_rs2);
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io.ctrl.br_ltu := (ex_reg_rs1.toUFix < ex_reg_rs2.toUFix);
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io.ctrl.br_lt :=
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(~(ex_reg_rs1(63) ^ ex_reg_rs2(63)) & io.ctrl.br_ltu |
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ex_reg_rs1(63) & ~ex_reg_rs2(63)).toBool;
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// writeback select mux
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ex_wdata :=
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Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1,
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Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_reg_pc_plus4,
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Mux(ex_reg_ctrl_sel_wb === WB_ALU, ex_alu_out,
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Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
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Bits(0, 64))))).toBits;
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|
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// memory stage
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mem_reg_pc <== ex_reg_pc;
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mem_reg_pc_plus4 <== ex_reg_pc_plus4;
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mem_reg_waddr <== ex_reg_waddr;
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mem_reg_wdata <== ex_wdata;
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mem_reg_ctrl_ll_wb <== ex_reg_ctrl_ll_wb;
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mem_reg_raddr2 <== ex_reg_raddr2;
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|
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when (io.ctrl.killx) {
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mem_reg_ctrl_div_val <== Bool(false);
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mem_reg_ctrl_mul_val <== Bool(false);
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mem_reg_ctrl_wen <== Bool(false);
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mem_reg_ctrl_wen_pcr <== Bool(false);
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mem_reg_ctrl_exception <== Bool(false);
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}
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|
otherwise {
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mem_reg_ctrl_div_val <== ex_reg_ctrl_div_val;
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mem_reg_ctrl_mul_val <== ex_reg_ctrl_mul_val;
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mem_reg_ctrl_wen <== ex_reg_ctrl_wen;
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mem_reg_ctrl_wen_pcr <== ex_reg_ctrl_wen_pcr;
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mem_reg_ctrl_exception <== ex_reg_ctrl_exception;
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}
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|
|
|
// exception signal to control (for NPC select)
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|
io.ctrl.exception := mem_reg_ctrl_exception;
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// for load/use hazard detection (load byte/halfword)
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|
io.ctrl.mem_waddr := mem_reg_waddr;
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|
|
|
// moved to earlier in file
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|
// val mem_dmem_resp_data_w =
|
|
// Mux(io.dmem.resp_pos(2).toBool, io.dmem.resp_data(63, 32), io.dmem.resp_data(31, 0));
|
|
//
|
|
// val mem_dmem_resp_data =
|
|
// Mux(io.dmem.resp_type === MT_D, io.dmem.resp_data,
|
|
// Mux(io.dmem.resp_type === MT_W, Cat(Fill(32, mem_dmem_resp_data_w(31)), mem_dmem_resp_data_w)),
|
|
// Cat(UFix(0,32), mem_dmem_resp_data_w));
|
|
|
|
// writeback stage
|
|
r_dmem_resp_val <== io.dmem.resp_val;
|
|
r_dmem_resp_waddr <== io.dmem.resp_tag(4,0).toUFix;
|
|
r_dmem_resp_pos <== dmem_resp_pos;
|
|
r_dmem_resp_type <== dmem_resp_type;
|
|
r_dmem_resp_data <== mem_dmem_resp_data;
|
|
|
|
wb_reg_pc <== mem_reg_pc;
|
|
wb_reg_pc_plus4 <== mem_reg_pc_plus4;
|
|
wb_reg_waddr <== mem_reg_waddr;
|
|
wb_reg_wdata <== mem_reg_wdata;
|
|
wb_reg_ctrl_ll_wb <== mem_reg_ctrl_ll_wb;
|
|
wb_reg_raddr2 <== mem_reg_raddr2;
|
|
|
|
when (io.ctrl.killm) {
|
|
wb_reg_ctrl_div_val <== Bool(false);
|
|
wb_reg_ctrl_mul_val <== Bool(false);
|
|
wb_reg_ctrl_wen <== Bool(false);
|
|
wb_reg_ctrl_wen_pcr <== Bool(false);
|
|
}
|
|
otherwise {
|
|
wb_reg_ctrl_div_val <== mem_reg_ctrl_div_val;
|
|
wb_reg_ctrl_mul_val <== mem_reg_ctrl_mul_val;
|
|
wb_reg_ctrl_wen <== mem_reg_ctrl_wen;
|
|
wb_reg_ctrl_wen_pcr <== mem_reg_ctrl_wen_pcr;
|
|
}
|
|
|
|
// crossbar/sign extension for 8/16 bit loads
|
|
// val dmem_resp_data_h =
|
|
// Mux(r_dmem_resp_pos(1).toBool, r_dmem_resp_data(31, 16), r_dmem_resp_data(15, 0));
|
|
// val dmem_resp_data_b =
|
|
// Mux(r_dmem_resp_pos(0).toBool, dmem_resp_data_h(15, 8), dmem_resp_data_h(7, 0));
|
|
//
|
|
// val dmem_resp_data_final =
|
|
// Mux(r_dmem_resp_type === MT_B, Cat(Fill(56, dmem_resp_data_b(7)), dmem_resp_data_b),
|
|
// Mux(r_dmem_resp_type === MT_BU, Cat(UFix(0, 56), dmem_resp_data_b),
|
|
// Mux(r_dmem_resp_type === MT_H, Cat(Fill(48, dmem_resp_data_h(15)), dmem_resp_data_h),
|
|
// Mux(r_dmem_resp_type === MT_HU, Cat(UFix(0, 48), dmem_resp_data_h),
|
|
// Mux((r_dmem_resp_type === MT_W) ||
|
|
// (r_dmem_resp_type === MT_WU) ||
|
|
// (r_dmem_resp_type === MT_D), r_dmem_resp_data,
|
|
// UFix(0,64))))));
|
|
|
|
// regfile write
|
|
rfile.io.w0.addr := wb_reg_waddr;
|
|
rfile.io.w0.en := wb_reg_ctrl_wen | wb_reg_ctrl_ll_wb;
|
|
rfile.io.w0.data := wb_reg_wdata;
|
|
|
|
rfile.io.w1.addr := r_dmem_resp_waddr;
|
|
rfile.io.w1.en := r_dmem_resp_val;
|
|
rfile.io.w1.data := dmem_resp_data_final;
|
|
|
|
// scoreboard set (for D$ misses, div, mul)
|
|
io.ctrl.sboard_set := wb_reg_ctrl_div_val | wb_reg_ctrl_mul_val | io.ctrl.dcache_miss;
|
|
io.ctrl.sboard_seta := wb_reg_waddr;
|
|
|
|
// scoreboard clear (for div/mul and D$ load miss writebacks)
|
|
io.ctrl.sboard_clr0 := wb_reg_ctrl_ll_wb;
|
|
io.ctrl.sboard_clr0a := wb_reg_waddr;
|
|
io.ctrl.sboard_clr1 := r_dmem_resp_val;
|
|
io.ctrl.sboard_clr1a := r_dmem_resp_waddr;
|
|
|
|
// processor control regfile write
|
|
pcr.io.w.addr := wb_reg_raddr2;
|
|
pcr.io.w.en := wb_reg_ctrl_wen_pcr;
|
|
pcr.io.w.data := wb_reg_wdata;
|
|
|
|
}
|
|
|
|
}
|